The power of functional scaling: Beyond the power consumption challenge and the scaling roadmap

IEEE Circuits and Devices Magazine

Volumn 21, Issue 1, 2005, Pages 27-35

  Chin, Albert ^a,b   McAlister, Séan P ^c  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c NATIONAL RESEARCH COUNCIL CANADA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CRYSTAL LATTICES; CURRENT DENSITY; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT MANUFACTURE; LEAKAGE CURRENTS; LOW TEMPERATURE EFFECTS; MOSFET DEVICES; SEMICONDUCTING GALLIUM ARSENIDE; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES;

DRIVE CURRENTS; GERMANIUM-ON-INSULATOR FIELD EFFECT TRANSISTORS; INTEGRATION DENSITY; POWER DISSIPATION; SCALING; SILICON DEVICES; VLSI STRUCTURE;

VLSI CIRCUITS;

EID: 13644276186     PISSN: 87553996     EISSN: None     Source Type: Journal    
DOI: 10.1109/MCD.2005.1388766     Document Type: Article

References (32)

1. T. Chuang, K. Bernstein, R. Joshi, R. Puri, K. Kim, E.J. Nowak, T. Ludwig, and I. Aller, "Scaling planar silicon devices," IEEE Circuit Devices Mag., vol. 20, pp. 6-19, Jan./Feb. 2004.
2. L. Chang, K.-Y. Choi, J. Kedzierski, N. Lindert, P. Xuan, J. Bokor, C. Hu, and T.-J. King, "Moore's law lives on" IEEE Circuits Devices Mag., vol. 19, pp. 35-42, Jan. 2003.
3. D.J. Frank, "Power-constrained CMOS scaling," IBM J. Res. Dev., vol. 46, pp. 235-244, Mar./May 2002.
4. B. Doris, M. Ieong, T. Kanarsky, Y. Zhang, R.A. Roy, O. Dokumaci, Z. Ren, F.F. Jamin, L. Shi, W. Natzle, H.J. Huang, J. Mezzapelle, A. Mocuta, S. Womack, M. Gribelyuk, E.C. Jones, R.J. Miller, H.-S.P. Wong, and W. Haensch, "Extreme scaling with ultra-thin Si channel MOSFETs," in IEDM Tech. Dig. 2002, pp. 267-270.
5. N.S. Kim, T. Austin, D. Baauw, T. Mudge, K. Flautner, J.S. Hu, M.J. Irwin, M. Kandemir, and V. Narayanan, "Leakage current: Moore's law meets static power," Computer, vol. 36, no. 12, pp. 68-75, Dec. 2003.
6. M. Horowitz, and W. Dally, "How scaling will change processor architecture," in ISSCC Tech. Dig. 2004, pp. 132-133.
7. The International Technology Roadmap for Semiconductors, Interconnect Chapter, pp. 3-4, 2001.
8. M.I. Cohen and C. Jagadish, "It's all about speed," IEEE Circuits Devices Mag., vol. 19, pp. 38-43, Jan. 2004.
9. E. Bonny, "Technologies for very high bandwidth electrical interconnects between next generation VLSI circuits," in IEDM Tech. Dig. 2001, pp. 533-534.
10. B.H. Lee, L. Kang, W.J. Qi, R. Nieh, Y. Jeon, K. Onishi, and J.C. Lee, "Ultrathin hafnium oxide with low leakage and excellent reliability for alternative gate dielectric application," in IEDM Tech. Dig 1999, pp. 133-136.
11. 3 gate dielectrics with equivalent oxide thickness 5-10Å," in Tech. Dig, Symp. on VLSI 2000, pp. 16-17.
12. H. Iwai, S. Ohmi, S. Akama, C. Ohshima, A. Kikuchi, I. Kashiwagi, J. Taguchi, H. Yamamoto, J. Tonotani, Y. Kim, I. Ueda, A. Kuriyama, and Y. Yoshihara, "Advanced gate dielectric materials for sub-100 nm CMOS," in IEDM Tech. Dig. 2002, pp. 625-628.
13. S.J. Doh, H.-S. Jung, Y.-S. Kim, H.-J. Lim, J.P. Kim, J.H. Lee, J.-H. Lee, N.-I. Lee, H.-K. Kan, K.-P. Suh, S.G. Park, S.B. Kang, G.H. Choi, Y.-S. Chung, H.-S. Baikz, H.-S. Chang, M.-H. Cho, D.-W. Moon, H.B. Park, M. Cho, and C.S. Hwang, "Improvement of NBTI and electrical characteristics by ozone pre-treatment and PBTI issues in HfAlO(N) high-k gate dielectrics," in IEDM Tech. Dig. 2003, pp. 943-946.
14. 2 gate dielectrics," in IEDM Tech. Dig. 2003, pp. 938-942.
15. 3 gate dielectrics," in Tech. Dig. Symp. on VLSI 2003, pp. 119-120.
16. 3 /Ge-on-insulator MOSFETs," in IEDM Tech. Dig. 2003, pp. 319-322.
17. 2(Hf) dual gates and high-K dielectric on 1P6M-0.18 μm-CMOS," in IEDM Tech. Dig. 2004, pp. 181-184.
18. X. Yu, C.X. Zhu, X.P. Wang, M.F. Li, A. Chin, A. Du, W.D. Wang, and D.L. Kwong, "High mobility and excellent threshold voltage stability of NMOSFETs using HfTaO gate dielectrics," in IEDM Tech. Dig. 2004, pp. 110-111.
19. 2/TiN gate stack," Tech. Dig. IEDM 2003, pp. 653-656.
20. 2) polysilicon: A novel approach to very low-resistive gate (∼2Ω-cm) without metal CMP nor etching," in IEDM Tech. Dig. 2001, pp. 815-828.
21. Q. Xiang, J.S. Goo, J. Pan, B. Yu, S. Ahmed, J. Zhang, and M.-R. Lin, "Strained silicon NMOS with nickel-silicide metal gate," in Tech. Dig. Symp. on VLSI 2003, pp. 103-104.
22. 2 electrodes," in 9th IEEE Int. Symp. Applications Ferroelectrics (ISAF) 1994, pp. 547-550.
23. S. Zhu, J. Chen, M.-F. Li, S.J. Lee, J. Singh, C.X. Zhu, A. Du, C.H. Tung, A. Chin, and D.L. Kwong, "N-type Schottky barrier source/drain MOSFET using Ytterbium Silicide," IEEE Electron Device Lett., vol. 25, pp. 565-567, Aug. 2004.
24. T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, "A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors," in IEDM Tech. Dig. 2003, pp. 978-980.
25. M. Yang, M. Ieong, L. Shi, K. Chan, V. Chan, A. Chou, E. Gusev, K. Jenkins, D. Boyd, Y. Ninomiya, D. Pendleton, Y. Surpris, D. Heenan, J. Ott, K. Guarini, C. D'Emic, M. Cobb, P. Mooney, B. To, N. Rovedo, J. Benedict, R. Mo, and H. Ng, "High performance CMOS fabricated on hybrid substrate with different crystal orientations," in IEDM Tech. Dig. 2003, pp. 453-456.
26. K. Rim, K. Chan, L. Shi, D. Boyd, J. Ott, N. Klymko, F. Cardone, L. Tai, S. Koester, M. Cobb, D. Canaperi, B. To, E. Duch, I. Babich, R. Carruthers, P. Saunders, G. Walker, Y. Zhang, M. Steen, and M. Ieong, "Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs," in IEDM Tech. Dig. 2003, pp. 49-52.
27. S.J. Koester, J.D. Schuab, G. Dehlinger. J.O. Chu, Q.C. Ouyang, and A. Grill, "High-efficiency, Ge-on-SOI lateral PIN photodiodes with 29 GHz bandwidth," in Dig. Device Research Conf., 2004, pp 175-176.
28. M.C. King, M.T. Yang, C.W. Kuo, Y. Chang, and A. Chin, "RF noise scaling trend of MOSFETs from 0.5 μm to 0.13 μm technology nodes," Dig. IEEE MTT-S Int'l Microwave Symp., 2004, pp. 9-12.
29. A. Chin, K.T. Chan, H.C. Huang, C. Chen, V. Liang, J.K. Chen, S.C. Chien, S.W. Sun, D.S. Duh, W.J. Lin, C. Zhu, M.-F. Li, S.P. McAlister, and D.L. Kwong, "RF passive devices on Si with excellent performance close to ideal devices designed by Electro-Magnetic simulation," in IEDM Tech. Dig. 2003, pp. 375-378.
30. D.S. Yu, K.T. Chan, A. Chin, S.P. McAlister, C. Zhu, M.F. Li, and D.-L. Kwong, "Narrow-band band-pass filters on Silicon substrates at 30 GHz," in Dig. IEEE MTT-S Int. Microwave Symp., 2004, pp. 1467-1470.
31. T. Ohguro, K. Kojima, H.S. Momose, S. Nitta, T. Fukuda, T. Enda, and Y. Toyoshima, "Improvement of high resistivity substrate for future mixed analog-digital application," in Dig. Symp. on VLSI Tech. 2002, pp. 158-159.
32. M. Telford, "Stretching silicon's lifespan," III-Vs Rev., vol. 17, pp. 36-39, Sept./Oct. 2004.