Sol-compliant wafer-level package technologies

Semiconductor International

Volumn 25, Issue 4, 2002, Pages 61-64

  Bakir, Muhannad ^a   Mulé, Anthony ^a   Thacker, Hiren ^a   Kohl, Paul ^a   Martin, Kevin ^a   Meindl, James ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHI-TO-MODULE INTERCONNECTION; GIGASCALE INTEGRATION (GSI); GIGASCALE SYSTEM-ON-A-CHIP (GSOC); OPTICAL CLOCKS; SEA OF LEADS (SOL) TECHNOLOGY;

CLOCKS; COST EFFECTIVENESS; ELECTRIC RESISTANCE; FLIP CHIP DEVICES; INDUCTANCE; INSERTION LOSSES; INTEGRATED OPTOELECTRONICS; MICROWAVES; OPTICAL INTERCONNECTS; OPTICAL WAVEGUIDES; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE TESTING;

CHIP SCALE PACKAGES;

EID: 0141935091     PISSN: 01633767     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Review

References (11)

1. M.S. Bakir, et al, "Sea of Leads Characterization and Design for Compatibility for Board Level Optical Waveguide Interconnection," to be presented, IEEE Custom Integrated Circuits Conference, Orlando, Fla., May 2002.
2. 2001 International Technology Roadmap for Semiconductors (ITRS), SIA.
3. M.S. Bakir, et al, "Sea of Leads Ultra-High-Density Compliant WLP Technology," to be presented, 52nd Electronics and Components Technology Conf., San Diego, May 2002.
4. Z. Feng, et al, "RF and Mechanical Characterization of Flip-Chip Interconnects in CPW Circuits with Underfill," JEEE Trans. on Microwave Theory and Techniques, December 1998, p. 2269.
5. H. Kusamilsu, et al, "The Flip-Chip Bump Interconnection for Millimeter-Wave GaAs MMIC," IEEE Trans. Electron. Packaging Manufact., January 1999, p. 23.
6. H.A. Reed, et al, "Fabrication of Microchannels Using Polycarbonates as Sacrificial Materials," journal of Micromechanics and Microengineering, October 2001, p. 733.
7. P.J. Restle, et al, "A Clock Distribution Network for Microprocessors," JEEE J. Solid State Circuits,May 2001, p. 792.
8. A. Jain, et al, "Porous Silica Materials as Low-k Dielectrics for Electronic and Optical Interconnects," Thin Solid Films, Vol. 398-399, 2001, p. 513.
9. A.V. Mulé, et al, "Input Coupling and Guided-Wave Distribution Scheme for Board-Level Intra-Chip Optical Clock Distribution Network Using Volume Grating Coupler Technology," Proc. IEEE International Interconnect Technology Conf., San Francisco, June 2001, p. 128.
10. M.L. Bushnell and V.D. Agrawal, Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits, Kluwer Academic Publishers (Boston, 2000).
11. H.D. Thacker, et al, "Compliant Probe Substrates for Testing High Pin-Count Chip Scale Packages," to be presented, 52nd Electronics and Components Technology Conf., San Diego, May 2002.