On-wafer process for stress-free area array floating pads

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 4587, Issue , 2001, Pages 100-105

  Fillion, Raymond A ^a   Wojnarowski, Robert J ^a   Cole, Herbert ^a   Claydon, Glenn ^a  

^a GE GLOBAL RESEARCH   (United States)

Author keywords

Ball Grid Array; Chip Scale; Flip Chip; Floating Pads; Solder Fatigue

Indexed keywords

COST EFFECTIVENESS; FAILURE (MECHANICAL); FATIGUE OF MATERIALS; MULTICHIP MODULES; POLYMERS; RELIABILITY; SOLDERED JOINTS; STRESS ANALYSIS; STRESS RELIEF; THERMAL CYCLING; THERMAL EXPANSION;

FLOATING PADS; SOLDER FATIGUE;

FLIP CHIP DEVICES;

EID: 0035772473     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Paul H. Houston, et al, "Processing and Reliability of Low Cost Flip Chip Assemblies Implementing Fast-Flow, Snap Cure Underfills", SMTA International, San Jose, CA, Sept. 12-16, 1999, pp. 182-192.
2. Jon G. Aday, et al., "Flip Chip Chip Scale Packaging: Transferring the Flip Chip Density Requirements from the Motherboard to the Chip Carrier", International Conference on Multichip Modules and High Density Packaging, Denver CO, April 15-17, 1998, pp. 229-235.
3. Young Kim, et al, "CSP Design and Reliability: Lead Design Guide for Center Pad μBGA Package", SMTA Chip Scale Packaging Symposium, San Jose CA, Sept. 12-16, 1999, pp. 89-96.
4. Robert J. Wojnarowski, et al, "General Electric Floating Pad Technology for BGA and Other Mismatched CTE Interfaces", SMTA Chip Scale Packaging Symposium, San Jose CA, Sept. 12-16, 1999, pp. 7-11.
5. US Patent 5,900,674, Wojnarowski et al, "Interface Structures for Electronic Devices", May 4, 1999.
6. US Patent 5,938,452, Wojnarowski, "Flexible Interface Structures for Electronic Devices", Aug. 17, 1999.
7. US Patent 6,046,410, Wojnarowski et al, "Interface Structures for Electronic Devices", April 4, 2000.
8. US Patent 6,092,280, Wojnarowski, "Flexible Interface Structures for Electronic Devices", July 25, 1999.
9. Robert Fenton, et al., "Warpage Modeling and Measurement", SMTA Chip Scale Packaging Symposium, San Jose CA, Sept. 12-16, 1999, pp. 110-115.
10. Masako Watanabe et al., "Solder Joint Study of CSP for Use During the Transition Period to Lead Free Process", SMTA Chip Scale Packaging Symp., San Jose CA, Sept. 12-16, 1999, pp. 12-19.