Compliant probe substrates for testing high pin-count chip scale packages

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2002, Pages 1188-1193

  Thacker, Hiren D ^a   Bakir, Muhannad S ^a   Keezer, David C ^a   Martin, Kevin P ^a   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FABRICATION; INTERFACES (MATERIALS); PROBES; SILICON WAFERS; SUBSTRATES;

SYSTEM-ON-A-CHIP (SOC);

CHIP SCALE PACKAGES;

EID: 0036287404     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. Sea of leads ultra-high-density compliant wafer-level packaging technology
2. Electrical test strategies for a waferlevel batch packaging technology
3. Test support processors for enhanced testability of high performance circuits