Design and optimization of a novel compliant off-chip interconnect - One-Turn Helix

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2002, Pages 910-914

  Zhu, Qi ^a   Ma, Lunyu ^a   Sitaraman, Suresh K ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; OPTIMIZATION; RELIABILITY; SILICON WAFERS; SUBSTRATES; THERMAL EXPANSION;

OFF-CHIP INTERCONNECTS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036297129     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. Mechanical and preliminary electrical design of a novel compliant one-turn helix (OTH) interconnect