Gigascale integration (GSI) interconnect limits and N-tier multilevel interconnect architectural solutions

International Workshop on System-Level Interconnect Prediction (SLIP 2000)

Volumn , Issue , 2000, Pages 147-148

  Davis, Jeff A ^a   Venkatesan, Raguraman ^a   Bowman, Keith ^a   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FLIP FLOP CIRCUITS; INTERCONNECTION NETWORKS; LOGIC GATES; MINIATURE INSTRUMENTS; TRANSISTORS;

GIGASCALE INTEGRATION (GSI) INTERCONNECT LIMITS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034592342     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)