Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2002, Pages 98-103

  Hrkic, Milos ^a   Lillis, John ^a  

^a UNIVERSITY OF ILLINOIS AT CHICAGO   (United States)

Author keywords

Algorithms

Indexed keywords

DEGREES OF FREEDOM (MECHANICS); OPTIMIZATION; ROUTERS; TOPOLOGY; TREES (MATHEMATICS);

BUFFER TREE SYNTHESIS;

INTERCONNECTION NETWORKS;

EID: 0036374274     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/505411.505413     Document Type: Conference Paper

References (13)

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9. New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing
10. Buffered Steiner tree construction with wire sizing for interconnect layout optimization
11. Buffer placement in distributed RC-tree networks for minimal elmore delay
12. Simultaneous routing and buffer insertion with restrictions on buffer locations