River PLAs: A regular circuit structure

Proceedings - Design Automation Conference

Volumn , Issue , 2002, Pages 201-206

  Mo, Fan ^a   Brayton, Robert K ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Programmable Logic Array; River routing

Indexed keywords

ALGORITHMS; FIELD PROGRAMMABLE GATE ARRAYS; FLIP FLOP CIRCUITS; LOGIC DESIGN; OPTIMIZATION;

PROGRAMMABLE LOGIC ARRAYS (PLA);

VLSI CIRCUITS;

EID: 0036058078     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/513969.513970     Document Type: Conference Paper

References (10)

1. A design scheme for PLA-based control tables with reduced area and time-delay cost
2. Multiple-valued minimization for PLA optimization
3. A force-directed macro-cell placer
4. Multi-level logic synthesis
5. Xilinx datasheet
6. Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric