On integrating power and signal routing for shield count minimization in congested regions

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 4, 2003, Pages 437-445

  Saxena, Prashant ^a   Gupta, Satyanarayan ^b  

^a INTEL CORPORATION   (United States)

^b INTEL TECHNOLOGY INDIA PVT LTD   (India)

Author keywords

Crosstalk optimization; Layout; Noise; Power grid design; Routing; Shielding

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; CROSSTALK; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC WIRE; ESTIMATION; MICROPROCESSOR CHIPS; OPTIMIZATION; SWITCHING FUNCTIONS;

ADAPTIVE POWER ROUTING ALGORITHM; FINE-GRAINED POWER GRID; SIGNAL ROUTING;

ELECTRIC SHIELDING;

EID: 0037387781     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.809654     Document Type: Article

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