CMOS TECHNOLOGY SCALING, O.lpm AND BEYOND

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 555-558

  Davari, Bijan ^a  

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; ELECTRONICS INDUSTRY; FIELD EFFECT TRANSISTORS; LEAKAGE CURRENTS; LITHOGRAPHY; OPTIMIZATION; PERFORMANCE; SEMICONDUCTOR DOPING; SPECIFICATIONS;

CIRCUIT DENSITY; CMOS TECHNOLOGY; DEVICE SPEED; EFFECTIVE CHANNEL LENGTH; PERFORMANCE; POWER IMPROVEMENTS; POWER-DELAY PRODUCTS; SCALINGS; SPEED ENHANCEMENT; TECHNOLOGY SCALING;

SEMICONDUCTOR DEVICE MANUFACTURE; CMOS INTEGRATED CIRCUITS;

CMOS TECHNOLOGY SCALING; POWER SUPPLY VOLTAGE; SHALLOW TRENCH ISOLATION; SHORT CHANNEL EFFECT; SILICON CHIP;

EID: 0030403761     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.554044     Document Type: Conference Paper

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