Minimisation of power dissipation during test application in full-scan sequential circuits using primary input freezing

IEE Proceedings: Computers and Digital Techniques

Volumn 147, Issue 5, 2000, Pages 313-322

  Nicolici, N ^a   Ai Hashimi, B M ^a   Williams, A C ^a  

^a UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ENERGY DISSIPATION; FLIP FLOP CIRCUITS; FREEZING; POWER CONTROL; SIMULATED ANNEALING; TEST FACILITIES; VECTORS;

SCAN LATCHES;

SEQUENTIAL CIRCUITS;

EID: 0034266584     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:20000537     Document Type: Article

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