Reduction of power consumption during test application by test vector ordering

Electronics Letters

Volumn 33, Issue 21, 1997, Pages 1752-1754

  Girard, P ^a   Landrault, C ^a   Pravossoudovitch, S ^a   Severac, D ^a  

^a LIRMM   (France)

Author keywords

Circuit testing; VLSI

Indexed keywords

ALGORITHMS; INTEGRATED CIRCUIT TESTING; VECTORS;

TEST VECTOR ORDERING;

VLSI CIRCUITS;

EID: 0031561210     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19971225     Document Type: Article

References (3)

1. CHAKRAVARTY, s., and DABHOLKAR, V.P.: 'Minimising power dissipation in scan circuits during test application'. Int. Workshop Low-Power Design, April 1994, pp. 51-56
2. CHAKRAVARTY, S., and DABHOLKAR, V.P.: 'Two techniques for minimising power dissipation in scan circuits during test application'. Proc. Asian Test Symp., November 1994, pp. 324-329
3. European Silicon Structures ES2, process ECPD07, library databook