Optimal vector selection for low power BIST

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 1999, Pages 219-226

  Corno, Fulvio ^a   Rebaudengo, Maurizio ^a   Reorda, Matteo Sonza ^a   Violante, Massimo ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; ELECTRIC BATTERIES; ELECTRIC POWER UTILIZATION; INTEGRATED CIRCUIT TESTING; POWER CONTROL; SEQUENTIAL CIRCUITS; VECTORS;

FULL SCAN TESTING;

VLSI CIRCUITS;

EID: 0033337081     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)