Simultaneous module selection and scheduling for power-constrained testing of core based systems

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2000, Pages 462-467

  Ravikumar, C P ^a   Chandra, Gaurav ^a   Verma, Ashutosh ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUILT-IN SELF TEST; CONSTRAINT THEORY; SCHEDULING; SYSTEMS ANALYSIS;

CORE BASED SYSTEM; PATTERN GENERATORS; POWER CONSTRAINED TESTING; POWER DISSIPATION; SIGNATURE REGISTERS;

INTEGRATED CIRCUIT TESTING;

EID: 0033901706     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)