Oxynitridation using radical-oxygen and -nitrogen for high-performance and highly reliable n/pFETs

IEEE Transactions on Electron Devices

Volumn 49, Issue 10, 2002, Pages 1761-1767

  Togo, Mitsuhiro ^b   Watanabe, Koji ^b   Terai, Masayuki ^b   Kimura, Shigeru ^b   Yamamoto, Toyoji ^b   Tatsumi, Toru ^b   Mogami, Tohru ^a,b  

^a IEEE

^b NEC CORPORATION   (Japan)

Author keywords

Dielectric films; Electron cyclotron resonance; Leakage currents; MOSFETs; Nitrogen; Oxygen

Indexed keywords

DIELECTRIC FILMS; ELECTRON CYCLOTRON RESONANCE; EMISSION SPECTROSCOPY; GATES (TRANSISTOR); LEAKAGE CURRENTS; MASS SPECTROMETRY; NITRIDING; NITROGEN; OXIDATION; OXYGEN; SEMICONDUCTING SILICON COMPOUNDS; SILICA;

GATE DIELECTRIC; OXYNITRIDATION; SILICON OXYNITRIDE;

MOSFET DEVICES;

EID: 0036773422     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2002.803640     Document Type: Article

References (22)

1. H. S. Momose, M. Ono, T. Yoshitomi, T. Oghuro, S. Nakamura, M. Saito, and H. Iwai, "Tunneling gate oxide approach to ultra-high current drive in small-geometry MOSFETs," in IEDM Tech. Dig., 1994, pp. 593-596.
2. M. S. Krishnan, L. Chang, T.-J. King, J. Bokor, and C. Hu, "MOSFETs with 9 to 13 A thick gate oxides," in IEDM Tech. Dig., 1999, pp. 241-244.
3. C. T. Liu, E. J. Lloyd, Y. Ma, M. Du, R. L. Opila, and S. J. Hillenius, "High performance 0.2 μm CMOS with 25 A gate oxide grown on nitrogen implanted SI substrates," in IEDM Tech. Dig., 1996, pp. 499-502.
4. T. Sorsch, W. Timp, F. H. Baumann, K. H. A. Bogart, T. Boone, V. M. Donnelly, M. Green, K. Evans-Lutterodt, C. Y. Kim, S. Moccio, J. Rosamilia, J. Sapjeta, P. Silverman, B. Weir, and G. Timp, "Ultra-thin, 1.0-3.0 nm, gate oxides for high performance sub-100 nm technology," in VLSI Tech. Dig., 1998, pp. 222-223.
5. A. Ono, K. Fukasaku, T. Matsuda, T. Fukai, N. Ikezawa, K. Imai, and T. Horiuchi, "A 70 nm gate length CMOS technology with 1.0 V operation," in VLSI Tech. Dig., 2000, pp. 14-15.
6. G. Timp, A. Agarwal, F. H. Baumann, T. Boone, M. Buananno, R. Cirelli, V. Donnelly, M. Foad, D. Grant, M. Green, H. Gossmann, S. Hillenius, J. Jackson, D. Jacobson, R. Kleiman, A. Kornblit, F. Klemens, J. T.-C. Lee, W. Mansfield, S. Moccio, A. Murrell, M. O'Malley, J. Rosamilia, J. Sapjeta, P. Silverman, T. Sorsch, W. W. Tai, D. Tennant, H. Vuong, and B. Weir, "Low leakage, ultra-thin gate oxides for extremely high performance sub-100 nm nMOSFETs," in IEDM Tech. Dig., 1997, pp. 930-932.
7. T. Yamamoto, K. Uejima, and T. Mogami, "Impact of 1-2 nm gate oxide for sub-quarter micron dual gate CMOS," in Int. Conf. SSDM, 1999, pp. 114-115.
8. M. Togo, K. Watanabe, T. Yamamoto, N. Ikarashi, K. Shiba, T. Tatsumi, H. Ono, and T. Mogami, "Low-leakage and highly reliable 1.5 nm SiON gate-dielectric using radical oxynitridation for sub-0.1 μm CMOS," in VLSI Tech. Dig., 2000, pp. 116-117.
9. 2 density of low-leakage 1.6 nm gate-SiON for high-performance and highly reliable n/pFETs," in VLSI Tech. Dig., 2001, pp. 81-82.
10. H. Yang and G. Lucovsky, "Integration of ultrathin (1.6-2.0 nm) RPECVD oxynitride gate dielectrics into dual poly-Si gate submicron CMOSFETs," in IEDM Tech. Dig., 1999, pp. 245-248.
11. M. T. Takayanagi and Y. Toyoshima, "Importance of Si-N atomic configuration at the Si/oxynitride interfaces on the performance of scaled MOSFETs," in IEDM Tech. Dig., 1998, pp. 575-578.
12. T. Ishihara, K. Matsuzawa, M. Takayanagi, and S. Takagi, "Comprehensive understanding of electron and hole mobility limited by surface roughness scattering in pure oxides and oxynitrides based on correlation function of surface," in Int. Conf. SSDM, 2001, pp. 380-381.
13. 4 stack gate dielectrics on the process controllability and reliability in direct tunneling regime," in IEDM Tech. Dig., 1999, pp. 323-326.
14. 2O/NO oxynitrides," in IEDM Tech. Dig., 1996, pp. 331-334.
15. Y. Shi, X. Wang, and T.-P. Ma, "Electrical properties of high-quality ultrathin nitride/oxide stack dielectrics," IEEE Trans. Electron Devices, vol. 46, pp. 362-368, Feb. 1999.
16. Z. J. Ma, Z. H. Liu, J. T. Krick, H. J. Huang, Y. C. Cheng, C. Hu, and P. K. Ko, "Optimization of gate oxide N2O anneal for CMOSFETs at room and cryogenic temperatures," IEEE Trans. Electron Devices, vol. 41, pp. 1364-1371, Aug. 1994.
17. K. Watanabe, T. Tatsumi, and S. Kimura, "Ultrathin oxide film formation using radical oxygen in a UHV system," in MRS 1999 Spring Meeting Abstr., 1999, pp. 268-269.
18. K. Watanabe, M. Togo, and T. Tatsumi, "Controlling the concentration and position of nitrogen in ultrathin oxynitride films formed by using radical oxygen and nitrogen," in MRS 1999 Fall Meeting Abstr., 1999.
19. 2 on Si," Appl. Phys. Lett., vol. 73, no. 15, pp. 2131-2133, Oct. 1998.
20. 2 on Si," J. Vac. Sci. Technol. A, vol. 14, pp. 971-976, May/June 1996.
21. Z. Wang, C. G. Parker, D. W. Hodge, R. T. Croswell, N. Yang, V. Misra, and J. R. Hauser, "Effect of polysilicon gate type on the flatband voltage shift for ultrathin oxide-nitride gate stacks," IEEE Trans. Electron Device Lett., vol. 21, pp. 170-172, Apr. 2000.
22. S. Takagi, N. Yasuda, and A. Toriumi, "A new I-V model for stress-induced leakage current including inelastic tunneling," IEEE Trans. Electron Devices, vol. 46, pp. 348-354, Feb. 1999.