On the SiO2-based gate-dielectric scaling limit for low-standby power applications in the context of a 0.13 μm CMOS logic technology

IEEE Transactions on Electron Devices

Volumn 49, Issue 3, 2002, Pages 442-447

  Lin, Yo Sheng ^b,c   Huang, Huan Tsung ^a,b   Wu, Chung Cheng ^b   Leung, Ying Keung ^b   Pan, Hsu Yang ^b   Chang, Tse En ^b   Chen, Wei Ming ^b   Liaw, Jung Jih ^b   Diaz, Carlos H ^a,b  

^a IEEE

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^c NATIONAL CHI NAN UNIVERSITY   (Taiwan)

Author keywords

Gate dielectric; Low standby power; Scaling limit

Indexed keywords

FABRICATION; LEAKAGE CURRENTS; LOGIC DESIGN; LOGIC GATES; MOSFET DEVICES; RELIABILITY; SEMICONDUCTING SILICON COMPOUNDS; SILICA; STANDBY POWER SYSTEMS;

GATE-DIELECTRIC SCALING;

CMOS INTEGRATED CIRCUITS;

EID: 0036494453     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.987115     Document Type: Article

References (17)

1. A modular 0.13 μm bulk CMOS technology for high performance and low power applications
2. A versatile 0.13 μm CMOS platform technology supporting high performance and low power applications
3. A 0.13 μm CMOS technology with 193 nm lithography and Cu/Low-k for high performance applications
4. Corner-Field induced drain leakage in thin oxide MOSFET's
5. The impact of gate-induced drain leakage current on MOSFET scaling
6. CMOS scaling into the nanometer regime
7. Back-gate bias enhanced band-to-band tunneling leakage in scaled MOSFET's
8. A 0.18 μm CMOS logic technology with dual gate oxide and Low-k interconnect for high-performance and low-power applications
9. Ultra-low leakage 0.16 μm CMOS for low-standby power applications
10. Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime
11. Characterization and modeling of edge direct tunneling (EDT) leakage in ultrathin gate oxide MOSFET's
12. 1.5 nm direct-tunneling gate oxide Si MOSFET's
13. Analysis of tunneling currents and reliability of NMOSFETs with sub-2 nm gate oxides
14. Analytic model for direct tunneling current in polycrystalline silicon-gate metal-oxide-semiconductor devices
15. Modeling study of ultrathin gate oxides using direct tunneling current and capacitance-voltage measurements in MOS devices
16. Quantum-Mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's
17. Process toward 10 nm CMOS devices