A 2-V 300-MHz 1-Mb current-sensed double-density SRAM for low-power 0.3-μm CMOS/SIMOX ASICs

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 10, 2001, Pages 1524-1537

  Shibata, Nobutaro ^b   Watanabe, Mayumi ^c   Sato, Yasuhiro ^a,c   Ishihara, Takako ^c   Komine, Yukio ^c  

^a IEEE

^b Nippon Telegraph and Telegraph and Telephone East Corporation   (Japan)

^c NTT CORPORATION   (Japan)

Author keywords

Current sense; Double density cell; High speed; Low power; Low voltage; Multi VDD; Pseudomulti Vth CMOS; SIMOX; SOI; Squashed layout; SRAM

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; CURRENT VOLTAGE CHARACTERISTICS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; ION IMPLANTATION; MICROPROCESSOR CHIPS; OXYGEN; RESISTORS; SILICON ON INSULATOR TECHNOLOGY; TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

MEMORY CELLS;

STATIC RANDOM ACCESS STORAGE;

EID: 0035472556     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.953481     Document Type: Article

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