Suppression of parasitic bipolar action in ultra-thin-film fully-depleted CMOS/SIMOX devices by ar-ion implantation into source/drain regions

IEEE Transactions on Electron Devices

Volumn 45, Issue 5, 1998, Pages 1071-1076

  Ohno, Terukazu ^a   Takahashi, Mitsutoshi ^a   Kado, Yuichi ^a   Tsuchiya, Toshiaki ^a  

^a NTT CORPORATION   (Japan)

Author keywords

Integrated circuits; MOSFET's; Silicon on insulator technology

Indexed keywords

ARGON; CMOS INTEGRATED CIRCUITS; ELECTRIC BREAKDOWN OF SOLIDS; ION IMPLANTATION; LEAKAGE CURRENTS; MOSFET DEVICES; SEMICONDUCTOR DEVICE MANUFACTURE; ULTRATHIN FILMS;

FULLY DEPLETED (FD) DEVICES; PARASITIC BIPOLAR ACTION (PBA); SOURCE AND DRAIN (S/D) REGIONS;

THIN FILM DEVICES;

EID: 0032070051     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.669534     Document Type: Article

References (12)

1. J. P. Colinge, "SOI technology for deep submicron CMOS applications," in Proc. 4th Int. Symp. VLSI Sei. Technol. Electrochem. Soc., 1993, vol. 93. no. 13, pp. 39-54.
2. T. Tsuchiya, T. Ohno, and Y. Kado, "Present status and potential of subquarter-micron ultra-thin-film CMOS/SIMOX technology," in Proc. 6th Int. Symp. SOI Technol. and Devices, Electrochem. Soc., 1994, vol. 94. no. 11, pp. 401-112.
3. C.-E. D. Chen, M. Matloubian, R. Sundaresan, B.-Y. Mao, C. C. Wei, and G. Pollack, "Single-transistor latch in SOI MOSFET's," IEEE Electron Device Lett., vol. 9, pp. 636-638, Dec. 1988.
4. M. Yoshimi, M. Terauchi, A. Murakoshi, M. Takahashi, K. Matsuzawa, N. Shigyo, and Y. Ushiku, "Technology trends of silicon-oninsulator-Its advantages and problems to be solved," in IEDM Tech. Dig., 1994, pp. 429-132.
5. J. H. Sim, C. H. Choi, and K. Kim, "Elimination of parasitic bipolarinduced breakdown effects in ultrathin SOI MOSFET's using narrowbandgap-source (NBS) structure," IEEE Trans. Electron Devices, vol. 42, pp. 1495-1502, Aug. 1995.
6. L. J. McDaid, S. Hall, W. Eccleston, and J. C. Alderman, "Suppression of latch in MOSFET's by silicidation of source," Electron. Lett., vol. 27, no. 11, pp. 1003-1005, 1991.
7. K. Azuma, A. Kishi, M. Tanigawa, S. Kaneko, T. Naka, A. Ishihama, K. Iguchi, and K. Sakiyama, "Application of Ti salicide process on ultrathin SIMOX wafer," in Proc. 1995 IEEE Int. SOI Conf., pp. 30-31.
8. Y. Sato, T. Tsuchiya, T. Kosugi, and H. Ishii, "Characteristics of l/4-μm gate ultrathin-film MOSFET's/SIMOX with tungsten-deposited low-resistance source/drain," in Proc. 1995 IEEE Int. SOI Conf., pp. 28-29.
9. S. Nakashima, "High-quality low-dose SIMOX wafers," IEICE Trans. Electron., vol. E80-C, no. 3, pp. 364-369, 1997.
10. T. Ohno, Y. Kado, M. Harada, and T. Tsuchiya, "Experimental 0.25-μm gate fully-depleted CMOS/SIMOX process using a new two-step LOCOS isolation technique," IEEE Trans. Electron Devices, vol. 42, pp. 1481-1486, Aug. 1995.
11. T. Tsuchiya and T. Ohno, "New hot-carrier-degradation mode in thinfilm SOI nMOSFET's," IEEE Electron Device Lett., vol. 16, pp. 427-129, Oct. 1995.
12. Y. Kado, H. Inokawa, Y. Okazaki, T. Tsuchiya, Y. Kawai, M. Sato, Y. Sakakibara, S. Nakayama, H. Yamada, M. Kitamura, S. Nakashima, K. Nishimura, S. Date, M. Ino, K. Takeya, and T. Sakai, "Substantial advantage of fully-depleted CMOS/SIMOX devices as low-power, high-performance VLSI components compared with their bulk-CMOS counterpart," in IEDM Tech. Dig., 1995, pp. 635-638.