1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM with charge-recycling input/output buffers

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 6, 1999, Pages 866-877

  Shibata, Nobutaro ^a   Morimura, Hiroki ^a   Watanabe, Mayumi ^a,b  

^a NTT CORPORATION   (Japan)

^b Musashino Electrical Communication Lab   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT TESTING; LEAKAGE CURRENTS; LOGIC GATES; MOSFET DEVICES; NICKEL CADMIUM BATTERIES; THRESHOLD VOLTAGE;

CHARGE RECYCLING TECHNIQUE; DATA TRANSITION DETECTORS; INPUT OUTPUT BUFFERS; MEMORY CELLS; MULTITHRESHOLD VOLTAGE;

RANDOM ACCESS STORAGE;

EID: 0032669774     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.766821     Document Type: Article

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