16 GB/s, 0.18 μm cache tile for integrated L2 caches from 256 KB to 2 MB

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2000, Pages 228-231

  Miller, Jeffrey L ^a   Conary, James ^a   DiMarco, David ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; BUILT-IN SELF TEST; MICROPROCESSOR CHIPS;

CHARGE SHARE DATA SENSE; PROGRAMMABLE BUILTIN SELF TEST;

VLSI CIRCUITS;

EID: 0033725311     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)