A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 11, 1996, Pages 1618-1624

  Mizuno, Hiroyuki ^a,b   Matsuzaki, Nozomu ^b,c   Osada, Kenichi ^b,d,e   Shinbo, Toshinobu ^b,f   Ohki, Nagatoshi ^b,e,f   Ishida, Hiroshi ^b,e,g   Ishibashi, Koichiro ^a,b,h,i   Kure, Tokuo ^b,e,j,k  

^a IEEE

^b HITACHI LTD   (Japan)

^c TOHOKU UNIVERSITY   (Japan)

^d KEIO UNIVERSITY   (Japan)

^e JAPAN SOCIETY OF APPLIED PHYSICS   (Japan)

^f IWATE UNIVERSITY   (Japan)

^g KANAGAWA UNIVERSITY   (Japan)

^h SOPHIA UNIVERSITY   (Japan)

ⁱ TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^j Osaka City University   (Japan)

^k KYOTO UNIVERSITY   (Japan)

more..

Author keywords

[No Author keywords available]

Indexed keywords

ASSOCIATIVE STORAGE; CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT MANUFACTURE; MICROPROCESSOR CHIPS; SEMICONDUCTOR STORAGE;

DOMINO TAG COMPARATORS; POWER CONSUMPTION; SEPARATED BIT LINE MEMORY HIERARCHY ARCHITECTURE;

BUFFER STORAGE;

EID: 0030290831     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.1996.542306     Document Type: Article

References (8)

1. T. Sakata, M. Horiguchi, and K. Itoh, "Subthreshold-current reduction circuits for multi-gigabit DRAM's," in 1993 Symp. VLSI Circuits Dig. Tech. Papers, May 1993, pp. 45-46.
2. M. Horiguchi, T. Sakata, and K. Itoh, "Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's," in 1993 Symp. VLSI Circuits Dig. Tech. Papers, May 1993, pp. 47-48.
3. H. Mizuno and T. Nagano, "Driving source-line (DSL) cell architecture for sub-1-V high-speed low-power applications," in 1995 Symp. VLSI Circuits Dig. Tech. Papers, June 1995, pp. 25-26.
4. W. J. Bowhil et al., "A 300 MHz 64 b quad-issue CMOS RISC microprocessor," in 1995 ISSCC Dig. Tech. Papers, Feb. 1995, pp. 182-183.
5. N. Kushiyama et al., "A 295 MHz CMOS 1 M (x256) embedded SRAM using bi-directional read/write shared sense Amps and self-timed pulsed word-line drivers," in 1995 ISSCC Dig. Tech. Papers, Feb. 1995, pp. 304-305.
6. A. J. Smith, "Cache memories," Computing Surveys, vol. 14, pp. 473-530, Sept. 1982.
7. L. Liu, "Partial address directory for cache access," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 2, no. 2, pp. 226-240, June 1994.
8. D. Bearden et al., "A 133 MHz 64 b four-issue CMOS microprocessor," in 1995 ISSCC Dig. Tech. Papers, pp. 174-175, Feb. 1995.