Megabit-class size-configurable 250-MHz SRAM macrocells with a squashed-memory-cell architecture

IEICE Transactions on Electronics

Volumn E82-C, Issue 1, 1999, Pages 94-103

  Shibata, Nobutaro ^a   Inokawa, Hiroshi ^a   Tokunaga, Keiichiro ^a   Ohta, Soichi ^a  

^a NTT CORPORATION   (Japan)

Author keywords

Current sense amplifier; High speed; Lowpower; Macrocell; Per bitline architecture; Size configurable; Squashed memory cell; SRAM; Trench isolation

Indexed keywords

AMPLIFIERS (ELECTRONIC); BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ENERGY DISSIPATION; INTEGRATED CIRCUIT LAYOUT; MOSFET DEVICES; READOUT SYSTEMS;

CURRENT SENSE AMPLIFIER; MACROCELLS; SQUASHED MEMORY CELL ARCHITECTURE; STATIC RANDOM ACCESS STORAGE; TRENCH ISOLATION;

RANDOM ACCESS STORAGE;

EID: 0033337147     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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