1-V 100-MHz embedded SRAM techniques for battery-operated MTCMOS/SIMOX ASICs

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 10, 2000, Pages 1396-1407

  Shibata, Nobutaro ^a   Morimura, Hiroki ^b   Harada, Mitsuru ^b  

^a Sapporo Medical Center   (Japan)

^b NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; ELECTRIC LOSSES; GATES (TRANSISTOR); LEAKAGE CURRENTS; MOS DEVICES; NICKEL CADMIUM BATTERIES; RANDOM ACCESS STORAGE; SEMICONDUCTOR SWITCHES; THRESHOLD VOLTAGE;

EMBEDDED STATIC RANDOM ACCESS STORAGE; MULTITHRESHOLD VOLTAGE CMOS; PSEUDO TWO STAGE PIPELINE ARCHITECTURE; SEPARATION BY IMPLANTATION OXYGEN; SHORT CLOCKED WORDLINE SELECTION TIME; SINGLE FAN IN LOAD;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034293958     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.871315     Document Type: Article

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