Current-sensed SRAM techniques for megabit-class integration - progress in operating frequency by using hidden writing-recovery architecture

IEICE Transactions on Electronics

Volumn E82-C, Issue 11, 1999, Pages 2056-2064

  Shibata, Nobutaro ^a  

^a NTT CORPORATION   (Japan)

Author keywords

Current sense; High speed; Squashed memory cell; SRAM; Virtual gnd line; Writing recovery

Indexed keywords

EID: 0000263774     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (17)

1. K. Ando, K. Higeta, Y. Fujimura, K. Mori, M. Nakayama, H. Nambu, K. Miyamoto, and K. Yamaguchi, "A 0.9-nsaccess, 700-MHz SRAM macro using a configurable organization technique with an automatic timing adjuster," Symp. on VLSI Circuits, Dig. of Tech. Papers, pp.182-183, 1998.
2. H. Goto, H. Ohkubo, K. Kondou, M. Ohkawa, H. Mitani, S. Horiba, M. Soeda, F. Hayashi, Y. Hachiya, T. Shimizu, M. Ando, and Z. Matsuda, "A 3.3-V 12-ns 16-Mb CMOS SRAM," IEEE J. Solid-State Circuits, vol.SC-27, no. 11, pp. 1490-1496, Nov. 1992.
3. M. Matsumiya, S. Kawashima, M. Sakata, M. Ookura, T. Miyabo, T. Koga, K. Itabashi, K. Mizutani, H. Shimada, and N. Suzuki, "A 15-ns 16-Mb CMOS SRAM with inter-digitated bitline architecture," IEEE J. Solid-State Circuits, vol.SC-27, no.ll, pp.1497-1503, Nov. 1992.
4. K. Sasaki, K. Ueda, K. Takasugi, H. Toyoshima, K. Ishibashi, T. Yamanaka, N. Hashimoto, and N. Ohki, "A 16-Mb CMOS SRAM with a 2.3-/tm2 single-bitline memory cell," IEEE J. Solid-State Circuits, vol.SC-27, no.ll, pp.1125-1130, Nov. 1993.
5. B. Bateman, C. Freeman, J. Haibert, K. Hose, G. Pétrie, and E. Reese, "A 450-MHz 512-KB second-level cache with a 3.6-GB/s data bandwidth," ISSCC, Dig. of Tech. Papers, pp.358-359, Feb. 1998.
6. K. Seevinck, P. J. van Beers, and H. Ontrop, "Currentmode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's sense amplifier for fast CMOS SRAMs," IEEE J. Solid-State Circuits, vol.SC-26, no.4, pp.525-536, April 1991.
7. K. Sasaki, K. Ishibashi, K. Ueda, K. Komiyaji, T. Yamanaka, N. Hashimoto, H. Toyoshima, F. Kojima, and A. Shimizu, "A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier," IEEE J. Solid-State Circuits, vol.SC27, no.ll, pp.1511-1518, Nov. 1992.
8. K. Seno, K. Knorpp, L.L. Shu, N. Teshima, H. Kihara, H. Sato, F. Miyaji, M. Takeda, M. Sasaki, Y. Tomo, P.T. Chuang, and K. Kobayashi, "A 9-ns 16-Mb CMOS SRAM with offset-compensated current sense amplifier," IEEE J. Solid-State Circuits, vol.SC-28, no.ll, pp.11191124, Nov. 1993.
9. K. Ishibashi, K. Ueda, K. Takasugi, K. Komiyaji, H. Toyoshima, T. Yamanaka, A. Fukami, N. Hashimoto, N. Ooki, A. Shimizu, T. Hashimoto, T. Nagano, and T. Nishida, "A 6-ns 4-Mb CMOS SRAM with offsetvoltage-insensitive current sense amplifiers," Symp. on VLSI Circuits, Dig. of Tech. Papers, pp.107-108, May 1994. [10] S. Tanoi, Y. Tanaka, T. Tanabe, A. Kita, T. Inada, R. Hamazaki, Y. Ohtsuki, and M. Uesugi, "A 32-bank 256Mb DRAM with cache and TAG," IEEE J. Solid-State Circuits, vol.SC-29, pp. 1330-1335, Nov. 1994.
10. N. Shibata, "Current-sense amplifiers for low-voltage memories," IEICE Trans. Electron., vol.E79-C, no.8, pp.1120-, 1130, Aug. 199G.
11. N. Shibata, H. Inokawa, K. Tokunaga, and S. Ohta, "Megabit-class size-configurable 250-MHz SRAM macrocells with a squashed-memory-cell architecture," IEICE Trans. Electron., vol.E82-C, no.l, pp.94-104, Jan. 1999.
12. T. Watanabe, M. Hayashi, I. Sasaki, Y. Akatsuka, T. Tsujide, II. Yamamoto, O. Kudoh, S. Takahashi, and T. Hara, "A battery backup 64 K CMOS SRAM with double level aluminum technology," IEEE J. Solid-State Circuits, vol.SC-18, no.5, pp.494-498, Oct. 1983.
13. N. Shibata, "A switched virtual-GND level technique for fast and low power SRAMs," IEICE Trans. Electron., vol.ESO-C, no.12, pp.1598-1607, Dec. 1997.
14. N. Shibata, T. Ishihara, and J. Fujioka, "Performance es"timation of synchronous fast SRAM macrocells-Test chip design and evaluation with LSI test systems," IEICE Trans. vol.J79-D-I, no.12, pp.1171-1184, Dec. 199G.
15. N. Shibata and H. Morimura, "Size-configurable 200-MHz low-power SRAM macrocells for MPEG2 video-encoding LSIs-Performance enhancement with embedded registers," IEICE Trans. vol.J81-C-II, no.6, pp.550-559, June 1998. (Published in English by Scripta Technica, Inc.: Electronics and Communications in Japan, Part II: Electronics, vol.82, no.l, pp.1-10, Jan. 1999.)
16. N. Shibata and H. Katoh, "A size-configurable two-port SRAM macrocell with the power reduction architecture using a writing-enable signal," IEICE Trans. vol.J81-CII, no.8, pp.698-709, Aug. 1998. (Published in English by Scripta Technica, Inc.: Electronics and Communications in Japan, Part II: Electronics, vol.82, no.5, pp.1-12, May 1999.)
17. K. J. O'Connor, "The source sensed SRAM (S3) cell," Symp. on VLSI Circuits, Dig. of Tech. Papers, pp. 119-120, June 1994.