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Volumn E79-C, Issue 8, 1996, Pages 1120-1130

Current sense amplifiers for low-voltage memories

Author keywords

Amplifier; Current sensing; Low voltage; ROM; SRAM

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC IMPEDANCE; ELECTRIC RESISTANCE; MOS DEVICES; RANDOM ACCESS STORAGE; ROM; TRANSCONDUCTANCE;

EID: 0030219434     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (35)

References (11)
  • 1
    • 85051964495 scopus 로고
    • 1-V high speed digital circuit technology with 0.5-μm multi-threshold CMOS
    • Sept.
    • S. Muto, T. Douseki, Y. Matsuya, T. Aoki, and J. Yamada, "1-V high speed digital circuit technology with 0.5-μm multi-threshold CMOS," Proc. IEEE Int. ASIC Conf., pp. 186-189, Sept. 1993.
    • (1993) Proc. IEEE Int. ASIC Conf. , pp. 186-189
    • Muto, S.1    Douseki, T.2    Matsuya, Y.3    Aoki, T.4    Yamada, J.5
  • 2
    • 0026141225 scopus 로고    scopus 로고
    • Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's sense amplifier for fast CMOS SRAM's
    • K. Seevinck, P. J. van Beers, and H. Ontrop, "Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's sense amplifier for fast CMOS SRAM's," IEEE J. Solid-State Circuits, vol. 26, no. 4, pp. 525-536.
    • IEEE J. Solid-State Circuits , vol.26 , Issue.4 , pp. 525-536
    • Seevinck, K.1    Van Beers, P.J.2    Ontrop, H.3
  • 8
    • 33746242682 scopus 로고
    • A High-gain current-mode sense amplifier with transconductance enhancing technique
    • Sept.
    • N. Shibata, "A High-gain current-mode sense amplifier with transconductance enhancing technique," Proc. of the 1994 IEICE Fall Conf. C-522, p. 200, Sept. 1994.
    • (1994) Proc. of the 1994 IEICE Fall Conf. , vol.C-522 , pp. 200
    • Shibata, N.1
  • 9
    • 0344883674 scopus 로고
    • Fast ROM macrocells for ASIC's
    • Sept.
    • N. Shibata, "Fast ROM macrocells for ASIC's," IEICE Trans., vol. J78-C-II, pp. 473-481, Sept. 1995.
    • (1995) IEICE Trans. , vol.J78-C-II , pp. 473-481
    • Shibata, N.1
  • 10
    • 0027698221 scopus 로고
    • High-performance memory macrocells with row and column sliceable architecture
    • Nov.
    • N. Shibata, Y. Goto, and S. Date, "High-performance memory macrocells with row and column sliceable architecture," IEICE Trans., pp. 1641-1648, Nov. 1993.
    • (1993) IEICE Trans. , pp. 1641-1648
    • Shibata, N.1    Goto, Y.2    Date, S.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.