Shared-bitline SRAM cell architecture for 1-V ultra low-power word-bit configurable macrocells

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 1999, Pages 12-17

  Morimura, Hiroki ^a   Shigematsu, Satoshi ^a   Konaka, Shinsuke ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC LOSSES; FORMAL LOGIC; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; MULTIPLEXING EQUIPMENT; THRESHOLD VOLTAGE;

STATIC RANDOM ACCESS MEMORY (SRAM);

RANDOM ACCESS STORAGE;

EID: 0033362615     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (4)