450 MHz 512 kB second-level cache with a 3.6 GB/s data bandwidth

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1998, Pages 358-359

  Bateman, B ^a   Freeman, C ^a   Halbert, J ^a   Hose, K ^a   Petrie, G ^a   Reese, E ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASSOCIATIVE STORAGE; BANDWIDTH; BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; DATA TRANSFER; LOGIC CIRCUITS; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; PHASE LOCKED LOOPS; PROGRAM PROCESSORS; TIMING CIRCUITS;

PROGRAMMABLE BUILT IN SELF TESTS (PBIST); SET ASSOCIATIVE CACHE STATIC RANDOM ACCESS MEMORY (SRAM); WEAK WRITE TEST MODES (WWTM);

RANDOM ACCESS STORAGE;

EID: 0031685660     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)