1 V 46 ns 16 Mb SOI-DRAM with body control technique

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 40, Issue , 1997, Pages 68-69

  Shimomura, Ken'ichi ^a   Shimano, Hiroki ^a   Okuda, Fumihiro ^a   Sakashita, Narumi ^a   Yamaguchi, Yasuo ^a   Oashi, Toshiyuki ^a   Eimori, Takahisa ^a   Inuishi, Masahide ^a   Arimoto, Kazutami ^a   Maegawa, Shigeto ^a   Inoue, Yasuo ^a   Nishimura, Tadashi ^a   Komori, Shinji ^a   Kyuma, Kazuo ^a   Yasuoka, Akihiko ^a   Abe, Haruhiko ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CELLULAR ARRAYS; LEAKAGE CURRENTS; MOS DEVICES; SILICON ON INSULATOR TECHNOLOGY; TRANSISTORS; VOLTAGE CONTROL;

BODY PULSED SENSE (BPS) AMPLIFIER; BODY VOLTAGE CONTROL; DYNAMIC RANDOM ACCESS MEMORY (DRAM);

RANDOM ACCESS STORAGE;

EID: 0031069028     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)