Low-power multi-gigabit CMOS/SIMOX LSI design using two power supply voltages

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1999, Pages 25-26

  Ohtomo, Yusuke ^a   Sawada, Hirotoshi ^a   Ohno, Terukazu ^a   Sakakibara, Yutaka ^a   Sato, Yasuhiro ^a   Ishihara, Takako ^a   Matsuoka, Shinji ^a   Shimaya, Masakazu ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC CELL BLOCKS; LOW POWER CHARACTERISTICS; TWO POWER SUPPLY VOLTAGES; TWO SUPPLY VOLTAGE TECHNIQUE;

BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; MICROPROCESSOR CHIPS; THRESHOLD VOLTAGE;

LSI CIRCUITS;

EID: 0033280015     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)