Quantitative characterization of substrate noise for physical design guides in digital circuits

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2000, Pages 95-98

  Nagata, Makoto ^a   Nagai, Jin ^a   Morie, Takashi ^a   Iwata, Atsushi ^a  

^a HIROSHIMA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; MICROPROCESSOR CHIPS; NOISE ABATEMENT; SPURIOUS SIGNAL NOISE; SUBSTRATES; VLSI CIRCUITS; VOLTAGE MEASUREMENT;

SUBSTRATE NOISE; SYSTEM ON A CHIP;

DIGITAL INTEGRATED CIRCUITS;

EID: 0033697635     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)