A novel Si/SiGe heterojunction pMOSFET with reduced short-channel effects and enhanced drive current

IEEE Transactions on Electron Devices

Volumn 47, Issue 10, 2000, Pages 1943-1949

  Ouyang, Qiqing ^a,d   Chen, Xiangdong ^a   Mudanai, Sivakumar P ^b   Wang, Xin ^a   Kencke, David L ^c   Tasch, Al F ^a   Register, Leonard F ^b   Banerjee, Sanjay Kumar ^a  

^a IEEE   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c The University of Texas at Austin   (United States)

^d INTEL CORPORATION   (United States)

Author keywords

Device simulation; Heterojunction; Hole mobility enhancement; Sige; Sub 100 nm mosfets

Indexed keywords

HIGH DRIVE CURRENT; HOLE MOBILITY ENHANCEMENT; SHORT CHANNEL EFFECTS;

COMPUTER SIMULATION; ENERGY GAP; HETEROJUNCTIONS; HIGH ELECTRON MOBILITY TRANSISTORS; LEAKAGE CURRENTS; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE STRUCTURES; THRESHOLD VOLTAGE;

MOSFET DEVICES;

EID: 0034294298     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.870577     Document Type: Article

References (34)

1. The National Technology Roadmap for Semiconductors, 1999.
2. Y. Taur et al., "CMOS scaling into the nanometer regime," Proc. IEEE, vol. 85, pp. 486-504, 1997.
3. S. Thompson, P. Packan, and M. Bohr, "MOS scaling: Transistor challenges for the 21st century," Intel Technol. J., vol. Q3, 1998.
4. K. Ismail, J. O. Chu, and B. S. Meyerson, "High hole mobility in SiGe alloys for device applications,"Appl. Phys. Lett., vol. 64, pp. 3124-3126, 1994.
5. K. Ismail, "Si/SiGe high-speed field-effect transistors," in IEDM Tech. Dig., 1995, pp. 509-512.
6. M. Arafa et al, "A 70-GHz Ft low operating bias self aligned p-type SiGe MODFET," IEEE Electron Device Lett., vol. 17, pp. 586-588, 1996.
7. S. J. Koester, R.Hammond, and J.O. Chu, "Extremely high transconductance Ge/Si0.4Ge0.6 p-MODFET's grown by UHV-CVD," IEEE Electron Device Lett., vol. 21, pp. 110-112, Mar. 2000.
8. S. A. Hareland, A. F. Tasch, and C. M. Maziar, "New structural approach for reducing punchthrough current in deep submicrometer MOSFET's and extending MOSFET scaling," Electron. Lett., vol. 29, pp. 1894-1896, October 1993.
9. _, "Analysis of a heterojunction MOSFET structure for deep-submicron scaling," in Proc. 21st Int. Symp. Compound Semiconductors, Sept. 1994, pp. 18-22.
10. P. Verheyen et ai, "A vertical Si/Si-.Ge.,. heterojunction pMOSFET with reduced DIBE sensitivity, using a novel gate dielectric approach," in 1999 Int. Symp. VLSI Technology, Systems, and Applications, 1999, pp. 19-22.
11. X. Chen et al, "Vertical P-MOSFETS with heterojunction between source/drain and channel," in Device Research Conf. Dig., 2000, pp. 25-26.
12. Q. Ouyang et al, "Two-dimensional bandgap engineering in a novel Si/SiGe pMOSFET with enhanced device performance and scalability," in Proc. Int. Conf. Simulation of Semiconductor Process and Devices, Sept. 2000, to be published.
13. MINIMOS-NT. Vienna, Austria: Inst. Microelectron., TU Vienna, 1998.
14. T. Simlinger, M. Rottinger, and S. Selberherr, "A method for unified treatment of interface conditions suitable for device simulation," in Proc. Int. Conf. Simulation of Semiconductor Process and Devices, 1997, pp. 173-176.
15. S. Jallepalli et al., "Hole transport in silicon: Presenting a Monte Carlo model based on the pseudopotential band structures," J. Appl. Phys., vol. 81, p. 2204, 1997.
16. X. Wang, V Chandramouli, C. M. Maziar, and A. F. Tasch, "Simulation program suitable for hot carrier studies: An efficient multiband Monte Carlo model using both full and analytical band structure for silicon," J. Appl. Phys., vol. 71, p. 3339, 1993.
17. T. Manku et al., "Drift hole mobility in strained and unstrained doped Sii_j..Gex. alloys," IEEE Trans. Electron Devices, vol. 40, pp. 1990-1996, Nov. 1993.
18. D. M. Richey, J. D. Cressler, and A. J. Joseph, "Scaling issues and Ge profile optimization in advanced UHV/CVD SiGe HBT's," IEEE Trans. Electron Devices, vol. 44, pp. 432-140, Mar. 1997.
19. M. Lundstrom, "Elementary scattering theory of the Si MOSFET," IEEE Electron Device Lett., vol. 18, p. 361, July 1997
20. T.-J. King et al., "A polycrystalline-Sii_.,.Ge.r-gate CMOS technology," in IEDM Tech. Dig., 1990, pp. 253-256.
21. P.-E. Hellburg, S.-L. Zhang, and C. S. Peterson, "Work function of boron-doped polycrystalline Sii .Gex. films," IEEE Electron Device Lett., vol. 18, pp. 456-58, Sept. 1997.
22. M. Niwa, Y. Toyoshima, and S. Kawamura, "private communication," unpublished, Dec. 9, 1999.
23. M. Rodder et al., "A 0.10//m gate length CMOS technology with 30 A gate dielectric for 1.0V-1.5V applications," in IEDM Tech. Dig., 1997, pp. 223-226
24. S. Mudanai, H. Wang, S. A. Khan, and A. F. Tasch, "Design of an optimal 100 nm gate length PMOS transistor for desktop applications,", SEMATECH Sponsored Res. Prog. Rep., January 1999.
25. W.-C. Lee, B. Watson, T.-J. King, and C. Hu, "Enhancement of PMOS device performance with poly-SiGe gate," IEEE Electron Device Lett., vol. 20, pp. 232-234, May 1999.
26. H. Jiang and R. G. Elliman, "Electrical properties of GeSi surface- and buried -channel p-MOSFET's fabricated by Ge implantation," IEEE Trans. Electron Devices, vol. 43, pp. 97-103, 1996.
27. A. Sadek et al., "Design of Si/SiGe heterojunction complementary metal-oxide-semiconductor transistors," IEEE Trans. Electron Devices, vol. 43, pp. 1224-1232, Aug. 1996.
28. M. Yoshimi et al, "Suppression of the floating-body effect in SOI MOSFET's by the bandgap engineering method using a Sii_1.Ge1. source structure," IEEE Trans. Electron Devices, vol. 44, pp. 423-130, Mar. 1997.
29. A. Nishiyama, O. Arisumi, and M. Yoshimi, "Suppression of the floating-body effect in partially-depleted SOI MOSFET's with SiGe source structure and its mechanism," IEEE Trans. Electron Devices, vol. 44, pp. 2187-2192, Dec. 1997.
30. X. D. Chen et al., "SiGe heterojunction vertical P-MOSFET with Si cap," Appl. Phys. Lett., to be published.
31. S. John et al., "Heterostructure p-channel metal-oxide-semiconductor transistor utilizing a Sii_1._i/Ge1.Ci/ channel," Appl. Phys. Lett., vol. 74, p. 5, Apr. 1999.
32. K. Eberl et al., "Growth and strain compensation effects in the ternary Sii_1._i/Ge1.Cj, alloy system," Appl. Phys. Lett., vol. 60, pp. 3033-3035, 1992.
33. A. St. Amour et al, "Defect-free band-edge photo-luminescence and bandgap measurement of pseudomorphic Si,_T_vGeTCv alloy layers on Si (100)," Appl. Phys. Lett., vol. 67, pp. 3915-1917, 1995.
34. L. Lanzerotti, J. Sterm, E. Stach, R. Hull, T. Buyuklimanli, and C. Magee, "Suppression of boron transient enhanced diffusion in SiGe heterojunction bipolar transistors by carbon incorporation," Appl. Phys. Lett., vol. 70, p. 3125, 1997.