Design of Si/SiGe heterojunction complementary metal-oxide-semiconductor transistors

IEEE Transactions on Electron Devices

Volumn 43, Issue 8, 1996, Pages 1224-1232

  Sadek, A ^a   Ismail, K ^b   Armstrong, M A ^c   Antoniadis, D A ^a   Stern, F ^b  

^a CAIRO UNIVERSITY   (Egypt)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c USA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRON TRANSPORT PROPERTIES; HETEROJUNCTIONS; MATHEMATICAL MODELS; MOSFET DEVICES; MULTILAYERS; OSCILLATORS (ELECTRONIC); OXIDES; SEMICONDUCTING SILICON; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR QUANTUM WELLS;

HYDRODYNAMIC NUMERICAL SIMULATION; RING OSCILLATORS; TWO DIMENSIONAL DRIFT DIFFUSION;

CMOS INTEGRATED CIRCUITS;

EID: 0030213473     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.506773     Document Type: Article

References (25)

1. C. T. Sah, "Evolution of the MOS transistor-From conception to VLSI," in Proc. IEEE, 1988, vol. 76. pp. 1280-1326.
2. K. Ismail, S. F. Nelson, J. O. Chu, and B. S. Meyerson, "Electron transport properties in Si/SiGe heterosTructures: Measurements and device implications," Appl. Phys. Lett., vol. 63, pp. 660-662, 19°3.
3. K. Ismail, J. O. Chu, and B. S. Meyerson, "High hole mobility in SiGe alloys for device applications," Appl. Phys. Leu., vol. 64. pp. 3124-3126, 1994.
4. R. A. Kiehl, P. M. Solomon, and D. J. Frank, "Heterqjunction FEST's in III-V compounds," IBM J. Res. Develop., vol. 34, pp. 506-529, 1990.
5. D. K. Nayak, J. C. S. Woo, J. S. Park, K. L. Wang, and K. P. McWilliams, "Enhancement-mode quantum-well GeSi PMOS," IEEE Electron Device Lett., vol. 12. p. 154, 1991.
6. V. P. Kesan, S. Subbanna, P. J. Resile. M. J. Tejwani. J. M. Altken. S. S. lyer, and J. A. Ott, "High performance 0.25 μm p-MOSFET's with silicon-germanium channels for 300 K and 77 K operation,'" 1EDM'91 Tech. Dig., 1991., p. 25.
7. K. Bhaumik. Y. Shacham-Diamand, J. P. Noel, J. Bevk, and L. C. Feldman, "23 GHz JV room temperature SiGe quantum well />MOSFETs.'ïn 1993 Int. Semiconductor Device Research Syrnp., 1993, p. 349.
8. J. Welser, J. L. Hoyt, and J. F. Gibbons, "NMOS and PMOS transistors fabricated in strained silicon/relaxed silicon-germanium structures," IEDM Tech. Dig., 1992, p. 1000; J. Welser, J. L. Hoyt, and J. F. Gibbons, "Electron mobility enhancement in strained Si N-type metal-oxide-semiconductor field-effect transistors," IEEE Electron Device Lett., vol. 15, p. 100, 1994.
9. S. Verdonckt-Vanderbroek, E. F. Crabbe, B. S. Meyerson, D. L. Harame, P. J. Restle, J. M. C. Stork, and J. B. Johnson, "SiGe channel heterojunction p-MOSFET's," IEEE Trans. Electron Devices, vol. 41, p. 90, 1994.
10. A. Sadek, "Analytical modeling of heterojunction field-effect transistors," Ph.D. Thesis, Cairo University, 1995; A. Sadek and K. Ismail, "Analytical modeling of Si/SiGe FET's," Solid State Electron., vol, 38, pp. 1969-1971, 1995.
11. MEDICI User's Manual, TMA Associates, Palo Alto, CA, 1992.
12. S. E. Laux and F. Stern, "Electron states in narrow gate-induced channels in Si," Appl. Phys. Lett., vol. 49, pp. 91-93, 1986.
13. B. S. Meyerson, K. Uram, and F. K. LeGoues, "Cooperative growth phenomena in silicon/germanium low-tempcraturc epitaxy,'' Appl. Phys. Lett., vol. 53, pp. 2555-2557, 1988.
14. J. W. Matthews. Epitaxial Growth, Part B. New York: Academic, 1975.
15. y substrates," Phys. Rev. B.. vol. 48, pp. 14276-14287, 1993.
16. G. G. Shahidi, D. A, Antoniadis, and H. I. Smith, "Electron velocity overshoot at room and liquid nitrogen temperatures in Si inversion layers," IEEE Electron Device Lett, vol. 9, pp. 94-96, 1988.
17. T. Yamada, J. R. Zhou, H. Miyata, and D. K. Ferry, "In-plane transport properties of Si/SiGe structure and its FET performance by computer simulation," IEEE Trans. Electron Devices, vol. 41, pp. I513-1522, 1994.
18. M. R. Pinto, E. Sangiorgi, and J. Bude, "Silicon MOS transconductance scaling in the overshoot regime," IEEE Electron Device Lett., vol. 14, pp. 375-378, 1993.
19. M. Iwase, T. Mizuno, M. Takahashi, H. Niiyama, M. Fukumoto, K. Ishida, S. Inaba, Y. Takigami, A. Sanda, A. Toriuml, and M. Yoshimi." IEEE Electron Device Lett., vol. 14, pp. 51-53, 1993.
20. H. Hanafi, P. Coane, A. Dally, T. Lii, and D. Mastin, "The design, fabrication and characterization of 0.15 μm MOS devices," in Proc. European Solid-State Device Research Conf., ESSDERC'93, Grenoble, France.
21. W. Chang, B. Davari, M. R. Wordeman, Y. Taur, C. Hsu, and D. Rodriguez, ''A high-performance 0.25 μm CMOS technology: I-Design and characterization," IEEE Trans. Electron Devices, vol. 39, pp. 959-966, 1992.
22. H. Hu, J. Jacobs, L. T. Su, and D. A. Antoniadis, "A study of deepsubmicron MOSFET scaling based on experiment and simulation," IEEE Trans. Electron Devices, vol. 42, pp. 669-677, 1995.
23. HSPICE User's Manual, Meta-Software, Campbell, CA, 1992.
24. K. Ismail, J. O. Chu, K. L. Saenger, and B. S. Meyerson, Appl. Phys. Lett., vol. 65, p. 1248, 1994.
25. W.-H. Chang, B. Davari, M. R. Wordeman, Y. Taur, C. C.-H. Hsu, and M. D. Rodriguez, IEEE Trans. Electron Devices, vol. 39, p. 959, 1992.