Enhancement of PMOS device performance with Poly-SiGe gate

IEEE Electron Device Letters

Volumn 20, Issue 5, 1999, Pages 232-234

  Lee, Wen Chin ^a   Watson, Bryan ^b   King, Tsu Jae ^a   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b Center of Excellence for Tactical and Advanced Communications Technologies   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CARRIER MOBILITY; CHEMICAL VAPOR DEPOSITION; GATES (TRANSISTOR); MATHEMATICAL MODELS; PERFORMANCE; SEMICONDUCTING SILICON; SILICON WAFERS; SPECTROMETRY; THRESHOLD VOLTAGE;

GATE DEPLETION EFFECT; HOLE MOBILITY; POLY SILICON GERMANIUM;

MOS DEVICES;

EID: 0032649564     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.761024     Document Type: Article

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