1C test using the energy consumption ratio

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 1, 2000, Pages 129-141

  Jiang, Wanli ^a   Vinnakota, Bapiraju ^b  

^a BOSTON SCIENTIFIC CORPORATION   (United States)

^b University of Minnesota   (United States)

Author keywords

1C test; Dynamic current test; Fault simulation; Process variation; Ratio test

Indexed keywords

COMPUTER SIMULATION; ELECTRIC FAULT CURRENTS; INTEGRATED CIRCUIT LAYOUT;

DYNAMIC CURRENT TEST; ENERGY CONSUMPTION RATIO;

INTEGRATED CIRCUIT TESTING;

EID: 0033908160     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.822625     Document Type: Article

References (38)

1. [ l ] L. K. Horning, J. Soden, R. Fritzemeier, and C. Hawkins, "Measurement of quiescent power supply current for CMOS 1C's in production testing," in Proc. IEEE Int. Test Conf., 1987, pp. 300-309.
2. R. C. Aitken, "A comparison of defect models for fault location with Iddq measurements," in Proc. IEEE Int. Test Conf., 1992, pp. 778-787.
3. H. Kondo and K. T. Cheng, "Driving toward higher IODQ test quality for sequential circuits: A generalized fault model and its ATPG," in Digest of Technical Papers, ICCAD, 1996, pp. 228-232.
4. S. Chakravarty and P. J. Thadikaran, "Simulation and generation of IDDQ tests for bridging faults in combinational circuits," IEEE Trans. Comput., vol. 45, no. 10, pp. 1131-1140, Oct. 1996.
5. T. Chen, I. N. Hajj, E. M. Rudnick, and J. H. Patel, "An efficient IDDQ test generation scheme for bridging faults in CMOS digital circuits," in Digest of Papers, IEEE Int. Workshop on IDDQ Testing, 1996, pp. 74-78.
6. Y. Higami, T. Maeda, and K. Kinoshita, "Sequential circuit test generation for IDDQ testing of bridging faults," in Digest of Papers, IEEE Int. Workshop on IDDQ Testing, 1997, pp. 12-16.
7. J. T. Chang and E. J. McCluskey, "Detecting bridging faults in dynamic CMOS circuits," in Digest of Papers, IEEE Int. Workshop on IDDQ Testing, 1997, pp. 106-109.
8. T. W. Williams, R. Kapur, M. R. Mercer, R. H. Dennard, and W. Maly, "IDDQ testing for high performance CMOS-The next ten years," in Proc. European Design and Test Conf., 1996, pp. 578-583.
9. J. M. Soden and C. F. Hawkins, "!DDQ Testing: Issues present and future," IEEE Design and Test of Computers, vol. 13, no. 4, pp. 61-65, 1996.
10. A. D. Singh, "Comprehensive wafer-oriented test evaluation (WOTE) scheme for the IDDQ testing of deep sub-micron technologies," in Digest of Papers, IEEE Int. Workshop on IDDQ Testing, 1997, pp. 403.
11. M. Sachdev, "Deep sub-micron IDDQ testing: Issues and solutions," in Proc. European Design and Test Conf., 1997, pp. 271-278.
12. A. E. Gattiker and W. Maly, "Current signatures: Application," in Proc. IEEE Int. Test Conf.. 1997, pp. 156-165.
13. J. Beasely, H. Ramamurthy, J. Ramirez-Angulo, and M. Deyong, "Idd pulse response testing: A unified approach to testing digital and analogue IC's," Electronics Letters, pp. 2101-2103, Nov. 25, 1993.
14. S. Su, R. Makki, and T. Nagle, "Transient power supply current monitoring-A new test method for CMOS VLSI circuits," J. Electron. Test.: Theory Applicat., pp. 2313, Feb. 1995.
15. J. A. Segura, M. Roca, D. Mateo, and A. Rubio, "An approach to dynamic power consumption testing of CMOS IC's," in Proc. IEEE VLSI Test Symp., Apr. 1995, pp. 95-100.
16. J. F. Plusquellic, D. M. Chiarulli, and S. P. Levitan, "Digital integrated circuit testing using transient signal analysis," in Proc. IEEE Int. Test Conf., 1996, pp. 48190.
17. C. Thibeault, "Detection of faults and defects using digital signal processing," in Proc. IEEE VLSI Test Symposium, 1995, pp. 262-267.
18. J. F Plusquellic, D. M. Chiarulli, and S. P. Levitan, "Identification of defective CMOS devices using correlation and regression analysis of frequency domain transient signal data," in Proc. IEEE Int. Test Conf., 1997, pp. 409.
19. A. Walker and P. K. Lala, "An approach for detecting bridging fault induced delay faults in static CMOS circuits using dynamic power supply current monitoring," in Digest of Papers, IEEE Int. Workshop on IDDQ Testing, 1997, pp. 73-77.
20. M. Sachdev, P. Janssen, and V. Zieren, "Defect detection with transient current testing and its potential for deep sub-micron CMOS IC's," in Proc. IEEE Int. Test Conf., 1998, pp. 204-213.
21. Y. Min, Z. Zhao, and Z. Li, "IDOT testing," in Proc. Asian Test Symp., 1997, pp. 378-382.
22. B. Vinnakota, "Monitoring power dissipation for fault detection," in Proc. IEEE VLSI Test Symp., Apr. 1996, pp. 48388.
23. B. Vinnakota, W.Wanli Jiang, and D. Sun, "Process-tolerant test with energy consumption ratio," in Proc. IEEE Int. Test Conf., Oct. 1998, pp. 1027-1036.
24. J. B. Shyu, G. C. Temes, and F Krummenarcher, "Random errors in MOS capacitors," IEEE J. Solid-State Circuits, pp. 1070-1075, 1982.
25. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Weibers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, pp. 1433-1440, Oct. 1989.
26. N. H. E. Weste and K. Eshraghian, CMOS VLSI Design: A Systems Perspective, 2nd ed. Reading, MA: Addison-Wesley, 1993.
27. F. Brglez, D. Bryan, and K. Kozminski, "Combinational profiles of sequential benchmark circuits," in Proc. IEEE Int. Symp. Circ. Syst., 1989, pp. 1929-1934.
28. C. Huang, B. Zhang, A. Deng, and B. Swirski, "The design and implementation of powermill," in IEEE/ACM Proc. Int. Symp. Low Power Design, 1995, pp. 105-109.
29. F. N. Najm, "A survey of power estimation techniques in VLSI circuits," IEEE Trans. VLSI Syst., vol. 2, no. 4, pp. 446-455, Dec. 1994.
30. C. Y. Tsui, M. Pedram, and A. Despain, "Efficient estimation of dynamic power dissipation under a real delay model," in Proc. IEEE Int. Conf. Computer-Aided Design, 1993, pp. 224-228.
31. D. Liu and C. Svensson, "Power consumption estimation in CMOS VLSI chips," IEEE J. Solid-State Circ., vol. 29, no. 6, pp. 663-670, 1994.
32. H. Veendrick, "Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits," IEEE J. Solid-State Circuits, vol. SC-19, no. 4, pp. 46873, Aug. 1984.
33. R. Burch, F Najm, P. Yang, and I. Hajj, "Pattern-independent current estimation for reliability analysis of CMOS circuits," in IEEE/'ACM Proc. Design Automation Conf., 1988, pp. 294-299.
34. A. Bogliolo, L. Benini, and G. Micheli, "Gate-level power and current simulation of CMOS integrated circuits," IEEE Trans. VLSI Syst., vol. 5, no. 4, pp. 47387, Dec. 1997.
35. J. Lin, T. Liu, and W. Shen, "A cell-based power estimation in CMOS combinational circuits," in Dig. Tech. Papers, IEEE Int. Conf. ComputerAided Design, 1994, pp. 304-309.
36. H. Sarin and A. McNelly, "A power modeling and characterization method for logic simulation," in Proc. IEEE Custom Integrated Circuits Conf., 1995, pp. 363-366.
37. J. Dévore and R. Peck, Statistics-The Exploration and Analysis of Data, 3rd éd. Belmont, CA: Wadsworth, 1997.
38. P. Maxwell, P. O'Neill, R. Aitken, R. Dudley, N. Jaarsma, M. Quach, and D. Wiseman, "Current Ratios: A Self-Scaling Technique for Production IDDQ testing," in Proc. ITC, 1999, pp. 738-746.