A Survey of Power Estimation Techniques in VLSI Circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 2, Issue 4, 1994, Pages 446-455

  Najm, Farid N ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; ELECTRIC NETWORK ANALYSIS; ELECTRIC POWER UTILIZATION; ENERGY DISSIPATION; INTEGRATED CIRCUIT LAYOUT; PARAMETER ESTIMATION;

POWER ESTIMATION;

VLSI CIRCUITS;

EID: 0028711580     PISSN: 10638210     EISSN: 15579999     Source Type: Journal    
DOI: 10.1109/92.335013     Document Type: Article

References (43)

1. R. W. Brodersen, A. Chandrakasan, and S. Sheng, “Technologies for personal communications,” 1991 Symp. VLSI Circ., Tokyo, Japan, pp. 5–9, 1991.
2. A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low-power CMOS digital design,” IEEE J. Solid-State Circ., vol. 27, no. 4, pp. 473–484, April 1992.
3. Workshop Working Group Reports, Semiconductor Industry Association, pp. 22–23, Nov. 17–19, 1992, Irving, TX.
4. S. Chowdhury and J. S. Barkatullah, “Estimation of maximum currents in MOS IC logic circuits,” IEEE Trans. Computer-Aided Design, vol. 9, no. 6, pp. 642–654, June 1990.
5. S. Devadas, K. Keutzer, and J. White, “Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation,” IEEE Trans. Computer-Aided Design, vol. 11, no. 3, pp. 373–383, March 1992.
6. H. Kriplani, F. Najm, and I. Hajj, “Maximum current estimation in CMOS circuits,” in 29th ACM/IEEE Design Automation Conf., Anaheim, CA, June 8–12, 1992, pp. 2–7.
7. H. J. M. Veendrick, “Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits,” IEEE J. Solid-State Circ., vol. SC-19, no. 4, pp. 468–473, Aug. 1984.
8. A. Shen, A. Ghosh, S. Devadas, and K. Keutzer, “On average power dissipation and random pattern testability of CMOS combinational logic networks,” in IEEE/ACM Int. Conf. Computer-Aided Design, Santa Clara, CA, Nov. 8–12, 1992, pp. 402-107.
9. K. P. Parker and E. J. McCluskey, “Probabilistic treatment of general combinational networks,” IEEE Trans. Comput., vol. C-24, pp. 668–670, June 1975.
10. F. Najm, “Transition density, a stochastic measure of activity in digital circuits,” in 28th ACM/IEEE Design Automation Conference, San Francisco, CA, June 17–21, 1991, pp. 644–649.
11. S. M. Kang, “Accurate simulation of power dissipation in VLSI circuits,” IEEE J. Solid-State Circ., vol. SC-21, no. 5, pp. 889–891, Oct. 1986.
12. G. Y. Yacoub and W. H. Ku, “An accurate simulation technique for short-circuit power dissipation based on current component isolation,” IEEE Int. Symp. Circuits and Syst., pp. 1157–1161, 1989.
13. A.-C. Deng, Y.-C. Shiau, and H.-H. Loh, “Time domain current wave-form simulation of CMOS circuits,” in IEEE Int. Conf Computer-Aided Design, Santa Clara, CA, Nov. 7–10, 1988, pp. 208–211.
14. R. Tjamstrom, “Power dissipation estimate by switch level simulation,” IEEE Int. Symp. Circuits and Syst., pp. 881–884, May 1989.
15. U. Jagau, “SIMCURRENT—An efficient program for the estimation of the current flow of complex CMOS circuits,” IEEE Int. Conf. Computer-Aided Design, Santa Clara, CA, Nov. 11–15, 1990, pp. 396–399.
16. T. H. Krodel, “PowerPlay-fast dynamic power estimation based on logic simulation,” IEEE Int. Conf. Computer Design, pp. 96–100, Oct. 1991.
17. L, Benini, M. Favalli, P. Olivo, and B. Ricco, “A novel approach to cost-effective estimate of power dissipation in CMOS ICs,” Europ. Design Automation Conf, 354–360, 1993.
18. F. Dresig, Ph. Lanches, O. Rettig, and U. G. Baitinger, “Simulation and reduction of CMOS power dissipation at logic level,” European Design Automation Conf, pp. 341–346, 1993.
19. M. A. Cirit, “Estimating dynamic power consumption of CMOS circuits,” IEEE Int. Conf. Computer-Aided Design, pp. 534–537, Nov. 9–12, 1987.
20. R. Burch, F. Najm, P. Yang, and D. Hocevar, “Pattern-independent current estimation for reliability analysis of CMOS circuits,” in 25th ACM/IEEE Design Automation Conf, Anaheim, CA, June 12–15, 1988, pp. 294–299.
21. F. Najm, R. Burch, P. Yang, and I. Hajj, “CREST—A current estimator for CMOS circuits,” IEEE Int. Conf. Computer-Aided Design, Santa Clara, CA, Nov. 7–10, 1988, pp. 204–207.
22. F. Najm, R. Burch, P. Yang, and I. Hajj, “Probabilistic simulation for reliability analysis of CMOS VLSI circuits,” IEEE Trans. Computer-Aided Design, vol. 9, no. 4, pp. 439–450, April 1990 (Errata in July 1990).
23. G. I. Stamoulis and I. N. Hajj, “Improved techniques for probabilistic simulation including signal correlation effects,” in 30th ACM/IEEE Design Automation Conf, 1993, pp. 379–383.
24. C.-Y. Tsui, M. Pedram, and A. M. Despain, “Efficient estimation of dynamic power consumption under a real delay model,” IEEE Int. Conf. Computer-Aided Design, Santa Clara, CA, Nov. 7–11, 1993, pp. 224–228.
25. F. Najm, “Transition density: a new measure of activity in digital circuits,” IEEE Trans. Computer-Aided Design, vol. 12, no. 2, pp. 310–323, Feb. 1993.
26. F. Najm “Improved estimation of the switching activity for reliability prediction in VLSI circuits,” IEEE Custom Integrated Circuits Conf, San Diego, CA, May 1–4, 1994, pp. 17.7.1-17.7.4.
27. F. Najm, “Low-pass filter for computing the transition density in digital circuits,” IEEE Trans. Computer-Aided Design, vol. 13, no. 9, pp. 1123–1131, September 1994.
28. A. Ghosh, S. Devadas, K. Keutzer, and J. White, “Estimation of average switching activity in combinational and sequential circuits,” 29th ACM/IEEE Design Automation Conf, Anaheim, CA, June 8–12, 1992, pp. 253–259.
29. C. M. Huizer, “Power dissipation analysis of CMOS VLSI circuits by means of switch-level simulation,” in IEEE Europ. Solid-State Circ. Conf., Grenoble, France, 1990, pp. 61–64.
30. R. Burch, F. Najm, P. Yang, and T. Trick, “McPOWER: A Monte Carlo approach to power estimation,” IEEE/ACM Int. Conf. Computer-Aided Design, Santa Clara, CA, Nov. 8–12, 1992, pp. 90–97.
31. R. Burch, F. Najm, P. Yang, and T. Trick, “A Monte Carlo approach for power estimation,” IEEE Trans. VLSI Syst., vol. 1, no. 1, pp. 63–71, Mar. 1993.
32. M. Xakellis and F. Najm, “Statistical estimation of the switching activity in digital circuits,” in 31st ACM/IEEE Design Automation Conf, San Diego, CA, 1994, pp. 728–733.
33. S. M. Ross, Stochastic Processes. New York: Wiley, 1983
34. A. Papoulis, Probability, Random Variables and Stochastic Processes, 2nd ed. New York: McGraw-Hill, 1984.
35. R. E. Bryant, “Graph-based algorithms for Boolean function manipulation,” IEEE Trans. Computer-Aided Design, pp. 677–691, Aug. 1986.
36. K. S. Brace, R. L. Rudell, and R. E. Bryant, “Efficient implementation of a BDD package,” in 27th ACM/IEEE Design Automation Conf., June 1990, pp. 40-45.
37. S. Chakravarty, “On the complexity of using BDDs for the synthesis and analysis of Boolean circuits,” in 27th Annual Allerton Conference on Communication, Control, and Computing, Monticello, IL, Sept. 27–29, 1989, pp. 730–739.
38. I. Miller and J. Freund, Probability and Statistics for Engineers, 3rd ed. Englewood Cliffs, NJ: Prentice-Hall, 1985.
39. B. Kapoor, “Improving the accuracy of circuit activity measurement,” in 31st ACM/IEEE Design Automation Conf, San Diego, CA, June 6–10, 1994, pp. 734-739.
40. A. A. Ismaeel and M. A. Breuer, “The probability of error detection in sequential circuits using random test vectors,” J. Electronic Testing, vol. 1, pp. 245–256, Jan. 1991.
41. G. D. Hachtel, E. Macii, A. Pardo, and F. Somenzi, “Probabilistic analysis of large finite state machines,” in 31st ACM/IEEE Design Automation Conf, June 6–10, 1994, San Diego, CA, pp. 270–275.
42. J. Monteiro and S. Devadas, “A methodology for efficient estimation of switching activity in sequential logic circuits,” in ACM/IEEE 31st Design Automation Conf, San Diego, CA, June 6–10, 1994, pp. 12–17.
43. C.-Y. Tsui, M. Pedram, and A. M. Despain, “Exact and approximate methods for calculating signal and transition probabilities in FSMs,” in ACM/IEEE 31st Design Automation Conf, San Diego, CA, June 6–10, 1994, pp. 18–23.