Simulation and generation of IDDQ tests for bridging faults in combinational circuits

IEEE Transactions on Computers

Volumn 45, Issue 10, 1996, Pages 1131-1140

  Chakravarty, Sreejit ^a,b   Thadikaran, Paul J ^a,b  

^a the State University of New York   (United States)

^b IEEE

Author keywords

Bridging faults; Fault simulation; IDDQ testing; Test generation

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; ELECTRIC CURRENT MEASUREMENT; LOGIC DESIGN; LOGIC GATES; PERFORMANCE; RANDOM PROCESSES; VECTORS;

BRIDGING FAULTS; FAULT SIMULATION; QUIESCENT POWER SUPPLY CURRENT; TEST GENERATION;

COMBINATORIAL CIRCUITS;

EID: 0030260163     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.543707     Document Type: Article

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