Gate-level power and current simulation of CMOS integrated circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 5, Issue 4, 1997, Pages 473-488

  Bogliolo, Alessandro ^b   Benini, Luca ^c   De Micheli, Giovanni ^a,c   Riccò, Bruno ^b  

^a IEEE

^b UNIVERSITY OF BOLOGNA   (Italy)

^c STANFORD UNIVERSITY   (United States)

Author keywords

Current waveform; Gate level simulation; Power consumption

Indexed keywords

COMPUTER SIMULATION; DATABASE SYSTEMS; ELECTRIC WAVEFORMS; LOGIC GATES; SEMICONDUCTOR DEVICE MODELS; TIME DOMAIN ANALYSIS; USER INTERFACES; WIDE AREA NETWORKS;

SOFTWARE PACKAGE VERILOG XL;

CMOS INTEGRATED CIRCUITS;

EID: 0031358166     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.645074     Document Type: Article

References (32)

1. C. Huang et al., "The design and implementation of Powermill," in Proc. IEEE Symp. Low Power Electronics, 1995, pp. 105-110.
2. F. Najm, "A survey of power estimation techniques in VLSI circuits," IEEE Trans. VLSI Syst., vol. 2, pp. 446-455, Dec. 1994.
3. C. Y. Tsui, M. Pedram, and A. Despain, "Efficient estimation of dynamic power dissipation under a real delay model," in Proc. IEEE Int. Conf. Computer-Aided Design, 1993, pp. 224-228.
4. R. Marculescu, D. Marculescu, and M. Pedram, "Logic level power estimation considering spatiotemporal correlations," in Proc. IEEE Int. Conf. Comput. Design, 1994, pp. 294-299.
5. D. Liu and C. Svensson, "Power consumption estimation in CMOS VLSI chips," IEEE J. Solid-State Circuit, vol. 29, no. 6, pp. 663-670, 1994.
6. P. Landman and J. Rabaey, "Architectural power analysis, the Dual Bit Type method," IEEE Trans. VLSI Syst., vol. 3, pp. 173-187, June 1995.
7. R. S. Martin and J. Knight, "Power-Profiler: Optimizing ASIC's power consumption at the behavioral level," in Proc. Design Automation Conf., 1995, pp. 42-47.
8. O. Coudert, R. Haddad, and K. Keutzer, "What is the state of the art in commercial eda tools for low power?," in Proc. Int. Symp. Low Power Electron. Design, 1996, pp. 181-187.
9. R. Burch, F. Najm, P. Yang, and I. Hajj, "Pattern independent current estimation for reliability analysis of CMOS circuits," in Proc. Design Automat. Conf., 1988, pp. 294-299.
10. H. Kriplani, F. N. Najm, and I. N. Hajj, "Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution," IEEE Trans. Computer-Aided Design, vol. 14, pp. 998-1012, Aug. 1995.
11. B. J. George et al., "Power analysis and characterization for semi-custom desing," in Proc. Int. Workshop Low Power Design, 1994, pp. 215-218.
12. J.-Y. Lin et al., "A cell-based power estimation in CMOS combinational circuits," in Proc. IEEE Int. Conf. Computer-Aided Design, 1994, pp. 304-309.
13. H. Sarin and A. McNelly, "A power modeling and characterization method for logic simulation," in Proc. IEEE Custom Integr. Circuits Conf., 1995, pp. 363-366.
14. S. Chowdhury and J. Barkatullah, "Current estimation in MOS IC logic circuits," in Proc. IEEE Int. Conf. Computer-Aided Design, 1988, pp. 212-215.
15. A. Deng, Y. Shiau, and K. Loh, "Time domain current waveform simulation of CMOS circuits," in Proc. IEEE Int. Conf. Computer-Aided Design, 1988, pp. 208-211.
16. S. Chowdury and J. Barkatullah, "Estimation of maximum currents in MOS IC logic circuits," IEEE Trans. Computer-Aided Design, vol. 9, pp. 642-654, June 1990.
17. U. Jagau, "SIMCURRENT - An efficient program for the estimation of the current flow of complex CMOS circuits," in Proc. IEEE Int. Conf. Computer-Aided Design, 1990, pp. 396-399.
18. F. Rouatbi, B. Haroun, and A. J. Al-Khalili, "Power estimation tool for sub-micron CMOS VLSI circuits," in Proc. IEEE Int. Conf. Computer-Aided Design, 1992, pp. 204-209.
19. A. Nabavi-Lishi and N. Rumin, "Delay and bus current evaluation in CMOS logic circuits," in Proc. IEEE Int. Conf. Computer-Aided Design, 1992, pp. 198-203.
20. A. Nabavi-Lishi and N. Rumin, "Inverter models of CMOS gates for supply current and delay evaluation," IEEE Trans. Computer-Aided Design, vol. 13, pp. 1271-1279, Oct. 1994.
21. A. Deng, "Power analysis for CMOS/BiCMOS circuits," in Proc. Int. Workshop on Low Power Design, 1994, pp. 3-8.
22. L. Benini, A. Bogliolo, and B. Ricce, "Distributed EDA tool integration: The PPP paradigm," in Proc. IEEE Int. Conf. Computer Design, 1996, pp. 448-453.
23. L. Benini, M. Favalli, and B. Riccò, "Analysis of hazard contribution to power dissipation in CMOS IC's," in Proc. Int. Workshop Low Power Design, 1994, pp. 27-32.
24. System Science's PowerSim, (http://techweb.cmp.com/ techweb/eet/eda/News/PowerSim.html).
25. Veritools' Power_Tool, (http://www.veritools-web.com/ power\_t.htm).
26. Synopys' DesignPower, (http://www.synopsys.com/products /power/power.html).
27. Senté's Watt Watcher/Gate, (http://www.powereda.com/wwinfo .htm).
28. Viewlogic's POET, (http://www.viewlogic.com/news/ prpoet.html).
29. R. E. Bryant, "Graph-based algorithms for boolean function manipulation," IEEE Trans. Comput., vol. C-35, pp. 677-691, Aug. 1986.
30. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, 2nd ed. Reading, PA: Addison-Wesley, 1992.
31. A. Bogliolo, L. Benini, G. D. Micheli, and B. Ricce, "Accurate logic level power estimation," in Proc. IEEE Symp. Low Power Electron., 1995, pp. 40-41.
32. T. Burd, "Current estimation in MOS IC logic circuits," Univ. of California at Berkeley, M.S. Rep. UCB/ERLM94/89.