Enhanced hetero structure field effect transistor CAD model suitable for simulation of mixed mode circuits

IEEE Transactions on Electron Devices

Volumn 46, Issue 8, 1999, Pages 1577-1588

  Ytterdal, Trond ^a   Fjeldly, Tor A ^b   Shur, Michael S ^c   Baier, Steven M ^a   Lucero, R ^d,e  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^b Nordic Semiconductor ASA   (Norway)

^c NORWEGIAN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Norway)

^d HONEYWELL TECHNOLOGY CENTER   (United States)

^e MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; CONVERGENCE OF NUMERICAL METHODS; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC RESISTANCE; HETEROJUNCTIONS; HYBRID INTEGRATED CIRCUITS; TRANSCONDUCTANCE;

DRAIN INDUCED BARRIER LOWERING; HETEROSTRUCTURE FIELD EFFECT TRANSISTOR; MIXED MODE CIRCUITS; SOFTWARE PACKAGE SPICE; UNIFIED CHARGE CONTROL MODELING; UNIVERSAL DRAIN CURRENT MODELING;

FIELD EFFECT TRANSISTORS;

EID: 0033169539     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.777144     Document Type: Article

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