Enhanced CAD model for gate leakage current in heterostructure field effect transistors

IEEE Transactions on Electron Devices

Volumn 43, Issue 6, 1996, Pages 845-851

  Lee, Kie Young ^a   Lund, Bjørnar ^a   Ytterdal, Trond ^b   Robertson, Perry ^c   Martinez, Edgar J ^c   Robertson, Jason ^d   Shur, Michael S ^e  

^a Chungbuk National University   (South Korea)

^b University of Virginia   (United States)

^c Rogaland Research   (Norway)

^d SANDIA NATIONAL LABORATORIES   (United States)

^e AIR FORCE RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CALCULATIONS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CURRENTS; EQUIVALENT CIRCUITS; GATES (TRANSISTOR); MATHEMATICAL MODELS; MESFET DEVICES; SEMICONDUCTOR DEVICE MANUFACTURE;

DRAIN CURRENT CHARACTERISTICS; ELECTRON TEMPERATURE; GATE CURRENT; HETEROSTRUCTURE FIELD EFFECT TRANSISTOR; HOT ELECTRON EFFECTS;

FIELD EFFECT TRANSISTORS;

EID: 0030172924     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.502114     Document Type: Article

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