Creating small fault dictionaries

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 18, Issue 2-3, 1999, Pages 346-356

  Chess, Brian ^a,b   Larrabee, Tracy ^a,b  

^a University of California Santa Cruz   (United States)

^b HEWLETT PACKARD COMPANY   (United States)

Author keywords

Data compression fault modeling; Fault dictionaries; Logic circuit fault diagnosis

Indexed keywords

DATA COMPRESSION FAULT MODELING; FAULT DICTIONARIES;

COMPUTER SIMULATION; DATA COMPRESSION; DATA REDUCTION; ENCODING (SYMBOLS); FAILURE ANALYSIS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033092663     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.748164     Document Type: Article

References (23)

1. M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital System Testing and Testable Design. New York: Computer Science Press 1990.
2. J. M. Acken and S. D. Millman, Accurate modeling and simulation o bridging faults, in Proc. Custom Integrated Circuits Conf., 1991, pp 17.4.1-17.4.4.
3. _, Fault model evolution for diagnosis: Accuracy vs precision, in Proc. Custom Integrated Circuits Conf., 1992, pp. 776-792.
4. R. C. Aitken and P. C. Maxwell, Better models or better algorithms? o techniques to improve fault diagnosis, Hewlett-Packard J., Feb. 1995.
5. V. Boppana and W. K. Fuchs, Fault dictionary compression by outpu sequence removal, in Proc. International Conf. on Computer-Aide Design, 1994, pp. 576-579.
6. V. Boppana, I. Hartanto, and W. K. Fuchs, Full fault dictionary storag based on labeled tree encoding, in Proc. VLSI Test Symp., 1996, pp 174-179.
7. M. Burrows and D. J. Wheeler, A block-sorting lossless data compression algorithm, Digital Equipment Corp., Systems Research Center Palo Alto, CA, Tech. Rep. 124, 1994.
8. B. Chess and T. Larrabee, Logic testing of bridging faults in CMO integrated circuits, IEEE Trans. Comput., pp. 338-345, Mar. 1998.
9. B. Chess, T. Larrabee, and C. Roth, On evaluating competing bridg fault models for CMOS IC's, in Proc. 1994 VLSI Test Symp., pp 446-451.
10. D. Feltham and W. Maly, Physically realistic fault models for analo CMOS neural networks, IEEE J. Solid-State Circuits, vol. 26, no. 9 pp. 1223-1229, Sept. 1991.
11. A. Jee and F. J. Ferguson, Carafe: An inductive fault analysis tool fo CMOS VLSI circuits, in Proc. IEEE VLSI Test Symp., 1993, pp. 92-98.
12. T. Larrabee, Test pattern generation using Boolean satisfiability, IEE Trans. Computer-Aided Design, pp. 4-15, Jan. 1992.
13. D. Lavo, B. Chess, T. Larrabee, and F. J. Ferguson, Diagnosin realistic bridging faults with single stuck-at information, IEEE Trans Computer-Aided Design, pp. 255-268, Mar. 1998.
14. T. Niermann and J. Patel, HITEC: A test generation package fo sequential circuits, in Proc. European Design Automation Conf., 1991 pp. 214-218.
15. I. Pomeranz and S. M. Reddy, On the generation of small dictionarie for fault location, in Proc. Int. Conf. on Computer-Aided Design, 1992 pp. 272-279.
16. J. Richman and K. R. Bowden, The modern fault dictionary, in Proc Int. Test Conf., 1985 pp. 696-702.
17. P. G. Ryan, W. K. Fuchs, and I. Pomeranz, Fault dictionary compression and equivalence class computation for sequential circuits, in Proc Int. Conf. on Computer-Aided Design, 1993, pp. 508-511.
18. J. A. Waicukauski, E. B. Eichelberger, D. O. Forlenza, E. Lindbloom and T. McCarthy, Fault simulation for structured VLSI, VLSI Design vol. VI, pp. 20-32, 1985.
19. L. W. Wang, M. R. Mercer, T. W. Williams, and S. W. Kao, On th decline of testing efficiency as fault coverage approaches 100%, i Proc. 1995 VLSI Test Symp., 1995, pp. 74-83.
20. T. A. Welch, A technique for high-performance data compression, IEEE Comput., vol. C17, pp. 8-19, June 1984.
21. J. Ziv and A. Lempel, A universal algorithm for sequential dat compression, IEEE Trans. Inform. Theory, vol. IT23, pp. 337-343 May 1977.
22. _, Compression of individual sequences via variable rate coding, IEEE Trans. Inform. Theory, vol. IT24, pp. 530-535, Sept. 1978.
23. F. Brglez and H. Fujiwara, A neutral netlist of 10 combinationa benchmark circuits and a target translator in fortran, presented at IEE Int. Symp. on Circuits and Systems, 1985.