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Volumn 26, Issue 9, 1991, Pages 1223-1229

Physically Realistic Fault Models for Analog CMOS Neural Networks

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, CMOS - DEFECTS; INTEGRATED CIRCUITS, LINEAR; INTEGRATED CIRCUITS, VLSI - DEFECTS;

EID: 0026220880     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.84938     Document Type: Article
Times cited : (35)

References (14)
  • 1
    • 27644592104 scopus 로고
    • Modeling of lithography related yield losses for CAD of VLSI circuits
    • July
    • W. Maly, “Modeling of lithography related yield losses for CAD of VLSI circuits,” IEEE Trans, Computer-Aided Design, vol. CAD-4, no. 4, pp. 166–177, July 1985.
    • (1985) IEEE Trans , vol.CAD-4 , Issue.4 , pp. 166-177
    • Maly, W.1
  • 2
    • 0021541891 scopus 로고
    • Systematic characterization of physical defects for fault analysis of MOS IC cells
    • W. Maly, J. Ferguson, and J. P. Shen, “Systematic characterization of physical defects for fault analysis of MOS IC cells,” in Proc. Int. Test Conf., 1984, pp. 390–399.
    • (1984) Proc. Int. Test Conf. , pp. 390-399
    • Maly, W.1    Ferguson, J.2    Shen, J.P.3
  • 3
    • 0022201294 scopus 로고
    • Inductive fault analysis of MOS integrated circuits
    • Dec.
    • J. P. Shen, W. Maly, and F. J. Ferguson, “Inductive fault analysis of MOS integrated circuits,” IEEE Design Test Mag., vol. 2, no. 6, pp. 13–26, Dec. 1985.
    • (1985) IEEE Design Test Mag. , vol.2 , Issue.6 , pp. 13-26
    • Shen, J.P.1    Maly, W.2    Ferguson, F.J.3
  • 4
    • 0022792790 scopus 로고
    • VLASIC: A catastrophic fault yield simulator for integrated circuits
    • D. M. H. Walker and S. W. Director, “VLASIC: A catastrophic fault yield simulator for integrated circuits,” IEEE Trans. Computer-Aided Design, vol. CAD-5, pp. 541–556, 1986.
    • (1986) IEEE Trans. Computer-Aided Design , vol.CAD-5 , pp. 541-556
    • Walker, D.M.H.1    Director, S.W.2
  • 5
    • 84941496876 scopus 로고    scopus 로고
    • ASIC neural networks and wafer-scale integration
    • D. B. I. Feltham and W. Maly, “ASIC neural networks and wafer-scale integration,” in preparation.
    • preparation.
    • Feltham, D.B.I.1    Maly, W.2
  • 6
    • 0020118274 scopus 로고
    • Neural networks and physical systems with emergent collective computational abilities
    • Apr.
    • J. J. Hopfield, “Neural networks and physical systems with emergent collective computational abilities,” Proc. Nat. Acad. Sci. U.S.A., vol. 79, pp. 2554–2558, Apr. 1982.
    • (1982) Proc. Nat. Acad. Sci. U.S.A. , vol.79 , pp. 2554-2558
    • Hopfield, J.J.1
  • 7
    • 0023979104 scopus 로고
    • VLSI implementation of a neural network model
    • Mar.
    • H. P. Graf, L. D. Jackel, and W. E. Hubbard, “VLSI implementation of a neural network model,” IEEE Comput.Mag., vol. 21, no. 3, pp. 41–49, Mar. 1988.
    • (1988) IEEE Comput.Mag. , vol.21 , Issue.3 , pp. 41-49
    • Graf, H.P.1    Jackel, L.D.2    Hubbard, W.E.3
  • 8
    • 0024700018 scopus 로고
    • Analog electronic neural networks
    • July
    • H. P. Graf and L. D. Jackel, “Analog electronic neural networks,” IEEE Circuits Devices Mag., vol. 5, no. 4, pp. 44–49, July 1989.
    • (1989) IEEE Circuits Devices Mag. , vol.5 , Issue.4 , pp. 44-49
    • Graf, H.P.1    Jackel, L.D.2
  • 9
    • 0346264613 scopus 로고
    • VLSI architectures for implementations of neural networks
    • Apr.
    • M. A. Sivlotti, M. R. Emerling, and C. A. Mead, “VLSI architectures for implementations of neural networks,” in AIP Conf. Proc. 151, Neural Networks for Computing (Snowbird, UT), Apr. 1986, pp. 409–413.
    • (1986) AIP Conf. Proc. 151 , pp. 409-413
    • Sivlotti, M.A.1    Emerling, M.R.2    Mead, C.A.3
  • 10
    • 0542400896 scopus 로고
    • Electronic hardware implementations of neural networks
    • Dec.
    • A. P. Thakoor, A. Moopenn, J. Lambe, and S. K. Khanna, “Electronic hardware implementations of neural networks,” Appl. Opt., vol. 26, no. 23, pp. 5085–5092, Dec. 1987.
    • (1987) Appl. Opt. , vol.26 , Issue.23 , pp. 5085-5092
    • Thakoor, A.P.1    Moopenn, A.2    Lambe, J.3    Khanna, S.K.4
  • 11
    • 0021466353 scopus 로고
    • Modeling of defects in integrated circuit photolithographic patterns
    • July
    • C. H. Stapper, “Modeling of defects in integrated circuit photolithographic patterns,” IBM J. Res. Develop., vol. 28, no. 4, pp. 461–474, July 1984.
    • (1984) IBM J. Res. Develop. , vol.28 , Issue.4 , pp. 461-474
    • Stapper, C.H.1
  • 12
    • 0022102574 scopus 로고
    • Modeling the critical area in yield forecasts
    • Aug.
    • A. V. Ferris-Prabhu, “Modeling the critical area in yield forecasts,” IEEE J. Solid-State Circuits, vol. SC-20, no. 4, pp. 874–878, Aug. 1985.
    • (1985) IEEE J. Solid-State Circuits , vol.SC-20 , Issue.4 , pp. 874-878
    • Ferris-Prabhu, A.V.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.