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1
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27644592104
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Modeling of lithography related yield losses for CAD of VLSI circuits
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July
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W. Maly, “Modeling of lithography related yield losses for CAD of VLSI circuits,” IEEE Trans, Computer-Aided Design, vol. CAD-4, no. 4, pp. 166–177, July 1985.
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IEEE Trans
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Maly, W.1
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2
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0021541891
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Systematic characterization of physical defects for fault analysis of MOS IC cells
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W. Maly, J. Ferguson, and J. P. Shen, “Systematic characterization of physical defects for fault analysis of MOS IC cells,” in Proc. Int. Test Conf., 1984, pp. 390–399.
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Proc. Int. Test Conf.
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Maly, W.1
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Shen, J.P.3
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3
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0022201294
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Inductive fault analysis of MOS integrated circuits
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Dec.
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J. P. Shen, W. Maly, and F. J. Ferguson, “Inductive fault analysis of MOS integrated circuits,” IEEE Design Test Mag., vol. 2, no. 6, pp. 13–26, Dec. 1985.
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IEEE Design Test Mag.
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Shen, J.P.1
Maly, W.2
Ferguson, F.J.3
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4
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0022792790
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VLASIC: A catastrophic fault yield simulator for integrated circuits
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D. M. H. Walker and S. W. Director, “VLASIC: A catastrophic fault yield simulator for integrated circuits,” IEEE Trans. Computer-Aided Design, vol. CAD-5, pp. 541–556, 1986.
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Walker, D.M.H.1
Director, S.W.2
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5
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84941496876
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ASIC neural networks and wafer-scale integration
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D. B. I. Feltham and W. Maly, “ASIC neural networks and wafer-scale integration,” in preparation.
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preparation.
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Feltham, D.B.I.1
Maly, W.2
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6
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0020118274
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Neural networks and physical systems with emergent collective computational abilities
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Apr.
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J. J. Hopfield, “Neural networks and physical systems with emergent collective computational abilities,” Proc. Nat. Acad. Sci. U.S.A., vol. 79, pp. 2554–2558, Apr. 1982.
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Hopfield, J.J.1
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VLSI implementation of a neural network model
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H. P. Graf, L. D. Jackel, and W. E. Hubbard, “VLSI implementation of a neural network model,” IEEE Comput.Mag., vol. 21, no. 3, pp. 41–49, Mar. 1988.
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Graf, H.P.1
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0024700018
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Analog electronic neural networks
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July
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H. P. Graf and L. D. Jackel, “Analog electronic neural networks,” IEEE Circuits Devices Mag., vol. 5, no. 4, pp. 44–49, July 1989.
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Graf, H.P.1
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VLSI architectures for implementations of neural networks
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Apr.
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M. A. Sivlotti, M. R. Emerling, and C. A. Mead, “VLSI architectures for implementations of neural networks,” in AIP Conf. Proc. 151, Neural Networks for Computing (Snowbird, UT), Apr. 1986, pp. 409–413.
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Sivlotti, M.A.1
Emerling, M.R.2
Mead, C.A.3
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10
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0542400896
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Electronic hardware implementations of neural networks
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Dec.
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A. P. Thakoor, A. Moopenn, J. Lambe, and S. K. Khanna, “Electronic hardware implementations of neural networks,” Appl. Opt., vol. 26, no. 23, pp. 5085–5092, Dec. 1987.
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Appl. Opt.
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Thakoor, A.P.1
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Khanna, S.K.4
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11
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0021466353
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Modeling of defects in integrated circuit photolithographic patterns
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July
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C. H. Stapper, “Modeling of defects in integrated circuit photolithographic patterns,” IBM J. Res. Develop., vol. 28, no. 4, pp. 461–474, July 1984.
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IBM J. Res. Develop.
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Stapper, C.H.1
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Modeling the critical area in yield forecasts
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Aug.
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A. V. Ferris-Prabhu, “Modeling the critical area in yield forecasts,” IEEE J. Solid-State Circuits, vol. SC-20, no. 4, pp. 874–878, Aug. 1985.
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