On evaluating competing bridge fault models for CMOS ICs

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1994, Pages 446-451

  Chess, Brian ^a   Roth, Carl ^a   Larrabee, Tracy ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BRIDGE CIRCUITS; DEFECTS; ELECTRIC FAULT CURRENTS; ELECTRIC FAULT LOCATION; ELECTRIC WIRING; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS;

BRIDGE FAULT MODELS; DEFECT COVERAGE;

CMOS INTEGRATED CIRCUITS;

EID: 0028742249     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)