Logic testing of bridging faults in CMOS integrated circuits

IEEE Transactions on Computers

Volumn 47, Issue 3, 1998, Pages 338-345

  Chess, Brian ^a,b   Larrabee, Tracy ^a,c  

^a IEEE   (United States)

^b HEWLETT PACKARD COMPANY   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Bridging faults; Fault models; Fault simulation; Realistic faults; Test pattern generation

Indexed keywords

COMPUTER SIMULATION; COMPUTER TESTING; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK TOPOLOGY; LOGIC CIRCUITS; MATHEMATICAL MODELS; THEOREM PROVING;

BRIDGING FAULTS; FAULT SIMULATION; TEST PATTERN GENERATION;

CMOS INTEGRATED CIRCUITS;

EID: 0032025009     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.660170     Document Type: Article

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