Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI

IEEE Transactions on Electron Devices

Volumn 46, Issue 1, 1999, Pages 173-183

  Ker, Ming Dou ^a,b  

^a IEEE   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

ESD; Esd clamp circuit; Snapback

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC DISCHARGES; ELECTRIC EQUIPMENT PROTECTION; ELECTRIC IMPEDANCE; ELECTRIC RESISTANCE; ELECTROSTATICS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS;

CLAMP CIRCUITS; ELECTROSTATIC DISCHARGE (ESD) PROTECTION;

VLSI CIRCUITS;

EID: 0032740282     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.737457     Document Type: Article

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