ESD protection to overcome internal gate-oxide damage on digital-analog interface of mixed-mode CMOS IC's

Microelectronics Reliability

Volumn 36, Issue 11-12 SPEC. ISS., 1996, Pages 1727-1730

  Ker, Ming Dou ^a   Yu, Ta Lee ^b  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^b WINBOND ELECTRONICS CORPORATION   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC DISCHARGES; ELECTROSTATICS; GATES (TRANSISTOR); INTEGRATED CIRCUIT TESTING; INTERFACES (MATERIALS); OXIDES;

ELECTROSTATIC DISCHARGE (ESD) PROTECTION; INTERNAL GATE OXIDE DAMAGE; DIGITAL ANALOG INTERFACES;

CMOS INTEGRATED CIRCUITS;

EID: 0030273995     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/0026-2714(96)00184-9     Document Type: Article

References (6)

1. C. Duvvury, R. N. Rountree, and O. Adams, "Internal chip ESD phenomena beyond the protection circuit," IEEE Trans. on Electron Devices, vol. 35, no. 12, pp. 2133-2139, Dec., 1988.
2. M. D. Jaffe and P. E. Cottrell, "Electrostatic discharge protection in a 4-Mbit DRAM," 1990 EOS/ESD symposium proceedings, EOS-12, pp. 218-223.
3. H. Terletzki, W. Nikutta, and W. Reczek, "Influence of the series resistance of on-chip power supply buses on internal device failure after ESD stress," IEEE Trans. on Electron Devices, vol. 40, no. 11, pp. 2081-2083, Nov., 1993.
4. C. Johnson, T. J. Maloney, and S. Qawami, "Two unusual HBM ESD failure mechanisms on a mature CMOS process," 1993 EOS/ESD Symp. Proc., EOS-15, pp.225-231.
5. M.-D. Ker, C.-Y. Wu, and H.-H. Chang, "Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI," IEEE Trans. Electron Devices, vol. 43, no. 4, pp.588-598, 1996.
6. EOS/ESD Standard for ESD Sensitivity Testing, EOS/ESD Association, Inc., NY., 1993.