Influence of the Series Resistance of On-Chip Power Supply Buses on Internal Device Failure After ESD Stress

IEEE Transactions on Electron Devices

Volumn 40, Issue 11, 1993, Pages 2081-2083

  Terletzki, H ^a   Nikutta, W ^a   Reczek, W ^a  

^a SIEMENS AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC DISCHARGES; ELECTRIC RESISTANCE; ELECTROSTATICS; FAILURE ANALYSIS; RANDOM ACCESS STORAGE; SEMICONDUCTOR DEVICES; STRESSES;

ELECTROSTATIC DISCHARGE; INTERNAL DEVICE FAILURE; ON CHIP POWER SUPPLY BUSES; SERIES RESISTANCE;

POWER SUPPLY CIRCUITS;

EID: 0027702157     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.239752     Document Type: Article

References (3)

1. C. Duvvury, T. Taylor, J. Lindgreen, J. Morris, and S. Kumar, “Input Protection Design for Overall Chip Reliability,” in Proc. 1989, EOS/ESD Symp., pp. 190–197.
2. K. L. Chen “The effects of interconnect process and snapback voltage on the ESD failure threshold of NMOS transistors,” IEEE Trans. Electron Devices, vol. ED-35, pp. 2140–2149, Dec. 1988.
3. C. Duvvury, R. N. Rountree, and L. S. White, “A summary of most effective electrostatic discharge protection circuits for MOS memories and their observed failure modes,” in Proc. 1983, EOS/ESD Symp., pp. 181–184.