Impact of technology scaling on ESD robustness and protection circuit design

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 1994, Pages 237-245

  Amerasekera, Ajith ^a   Duvvury, Charvaka ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC EQUIPMENT PROTECTION; ELECTROSTATICS; GATES (TRANSISTOR); MOS DEVICES; PERFORMANCE; SEMICONDUCTOR JUNCTIONS;

ELECTROSTATIC DISCHARGE; POLYSILICON GATE LENGTH; TECHNOLOGY SCALING;

ELECTRIC DISCHARGES;

EID: 0028732943     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (31)