Design methodology for optimizing gate driven ESD protection circuits in submicron CMOS processes

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 1997, Pages 230-239

  Chen, Julian Zhiliang ^a   Amerasekera, Ajith ^a   Duvvury, Charvaka ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC DISCHARGES; ELECTROSTATICS; GATES (TRANSISTOR); OPTIMIZATION;

ELECTROSTATIC DISCHARGE (ESD); SOFTWARE PACKAGE SPICE; SUBMICRON PROCESSES;

CMOS INTEGRATED CIRCUITS;

EID: 0031352418     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)