Design considerations of high-k gate dielectrics and metal gate electrodes for Sub-0.1 μm MOSFETs

European Solid-State Device Research Conference

Volumn , Issue , 1998, Pages 308-311

  Cheng, Baohong ^b   Cao, Min ^a   Voode, Paul Vande ^a   Greene, Wayne ^a   Stork, Hans ^a   Yu, Zhiping ^c   Woo, Jason C S ^b  

^a ULSI Research Laboratory Hewlett PackGrd Laboratories   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; DIELECTRIC DEVICES; DIELECTRIC MATERIALS; MOSFET DEVICES; QUANTUM THEORY;

DESIGN CONSIDERATIONS; DIELECTRIC PERMITTIVITIES; HIGH- K GATE DIELECTRICS; METAL GATE ELECTRODES; NUMERICAL SIMULATORS; QUANTUM MECHANICAL MODEL; SHORT-CHANNEL PERFORMANCE; SOURCE/DRAIN REGIONS;

GATE DIELECTRICS;

EID: 0346109453     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. S.-H Lo, et al., IEEE ED4 pp.206-208, 1997.
2. S. A. Campbell, et al., IEEE TED, pp.104-109, 1997.
3. C. HU, IIEDM, p. 319-322, 1996.
4. P. V. Voorde, et al., IEDMp. 811-814, 1996.
5. H. Shimada, et al., IEDM, p. 881-884. 1996