Gate Stack architecture analysis and channel engineering in deep sub-micron MOSFETs

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 38, Issue 4 B, 1999, Pages 2266-2271

  Inani, Anand ^a   Rao, Ramgopal Valipe ^b   Cheng, Baohong ^c   Woo, Jason ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

^c MOTOROLA INC   (United States)

Author keywords

Channel engineering; Deep submicron mosfet; Fringing fields; High K gate dielectrics; Super steep retrograde channel profile

Indexed keywords

EID: 0041565726     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.38.2266     Document Type: Article

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